Narayanan Vijaykrishnan

According to our database1, Narayanan Vijaykrishnan authored at least 425 papers between 1996 and 2019.

Collaborative distances:

Awards

ACM Fellow

ACM Fellow 2014, "For contributions to power estimation and optimization in the design of power-aware systems.".

Timeline

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Bibliography

2019
Utilization of Negative-Capacitance FETs to Boost Analog Circuit Performances.
IEEE Trans. VLSI Syst., 2019

ROBIN: Monolithic-3D SRAM for Enhanced Robustness with In-Memory Computation Support.
IEEE Trans. on Circuits and Systems, 2019

Computing With Networks of Oscillatory Dynamical Systems.
Proceedings of the IEEE, 2019

Going Vertical: The Future of Electronics.
IEEE Micro, 2019

Byzantine-Tolerant Inference in Distributed Deep Intelligent System: Challenges and Opportunities.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019

Design of 2T/Cell and 3T/Cell Nonvolatile Memories with Emerging Ferroelectric FETs.
IEEE Design & Test, 2019

Context-Aware Collaborative Object Recognition For Distributed Multi Camera Time Series Data.
Proceedings of the Tenth International Symposium on Information and Communication Technology, 2019

Monolithic-3D Integration Augmented Design Techniques for Computing in SRAMs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Programmable Non-Volatile Memory Design Featuring Reconfigurable In-Memory Operations.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Context-Aware Convolutional Neural Network over Distributed System in Collaborative Computing.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
Compact 3-D-SRAM Memory With Concurrent Row and Column Data Access Capability Using Sequential Monolithic 3-D Integration.
IEEE Trans. VLSI Syst., 2018

Symmetric 2-D-Memory Access to Multidimensional Data.
IEEE Trans. VLSI Syst., 2018

IAA: Incidental Approximate Architectures for Extremely Energy-Constrained Energy Harvesting Scenarios using IoT Nonvolatile Processors.
IEEE Micro, 2018

An Accuracy Tunable Non-Boolean Co-Processor Using Coupled Nano-Oscillators.
JETC, 2018

Noise Aware Power Adaptive Partitioned Deep Networks for Mobile Visual Assist Platforms.
Proceedings of the 31st IEEE International System-on-Chip Conference, 2018

Indoor Navigation using Text Extraction.
Proceedings of the 2018 IEEE International Workshop on Signal Processing Systems, 2018

MDACache: Caching for Multi-Dimensional-Access Memories.
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018

Harnessing Emerging Technology for Compute-in-Memory Support.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

A Power-Efficient Hybrid Architecture Design for Image Recognition Using CNNs.
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Dual Mode Ferroelectric Transistor based Non-Volatile Flip-Flops for Intermittently-Powered Systems.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018

A Monolithic-3D SRAM Design with Enhanced Robustness and In-Memory Computation Support.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018

Stochastic Functional Verification of DNN Design through Progressive Virtual Dataset Generation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Drones as collaborative sensors for image recognition.
Proceedings of the IEEE International Conference on Consumer Electronics, 2018

Heuristic Approximation of Early-Stage CNN Data Representation for Vision Intelligence Systems.
Proceedings of the 36th IEEE International Conference on Computer Design, 2018

Emerging reconfigurable nanotechnologies: can they support future electronics?
Proceedings of the International Conference on Computer-Aided Design, 2018

NEOFog: Nonvolatility-Exploiting Optimizations for Fog Computing.
Proceedings of the Twenty-Third International Conference on Architectural Support for Programming Languages and Operating Systems, 2018

2017
Dynamic Diagnosis for Defective Reconfigurable Single-Electron Transistor Arrays.
IEEE Trans. VLSI Syst., 2017

Dynamic Power and Energy Management for Energy Harvesting Nonvolatile Processor Systems.
ACM Trans. Embedded Comput. Syst., 2017

Maximum Energy Efficiency Tracking Circuits for Converter-Less Energy Harvesting Sensor Nodes.
IEEE Trans. on Circuits and Systems, 2017

Advancing Nonvolatile Computing With Nonvolatile NCFET Latches and Flip-Flops.
IEEE Trans. on Circuits and Systems, 2017

Always-On Speech Recognition Using TrueNorth, a Reconfigurable, Neurosynaptic Processor.
IEEE Trans. Computers, 2017

Third Eye: A Shopping Assistant for the Visually Impaired.
IEEE Computer, 2017

A Multitask Grocery Assist System for the Visually Impaired: Smart glasses, gloves, and shopping carts provide auditory and tactile feedback.
IEEE Consumer Electronics Magazine, 2017

Incidental computing on IoT nonvolatile processors.
Proceedings of the 50th Annual IEEE/ACM International Symposium on Microarchitecture, 2017

Improving FPGA Design with Monolithic 3D Integration Using High Dense Inter-Stack Via.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Harnessing ferroelectrics for non-volatile memories and logic.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017

Nonvolatile processors: Why is it trending?
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Co-training of Feature Extraction and Classification using Partitioned Convolutional Neural Networks.
Proceedings of the 54th Annual Design Automation Conference, 2017

The Third Eye: A Shopping Assistant for the Visually Impaired.
Proceedings of the 2017 CHI Conference on Human Factors in Computing Systems, 2017

Spendthrift: Machine learning based resource and frequency scaling for ambient energy harvesting nonvolatile processors.
Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016
A Saliency-Driven LCD Power Management System.
IEEE Trans. VLSI Syst., 2016

Exploration of Low-Power High-SFDR Current-Steering D/A Converter Design Using Steep-Slope Heterojunction Tunnel FETs.
IEEE Trans. VLSI Syst., 2016

Diagnosis and Synthesis for Defective Reconfigurable Single-Electron Transistor Arrays.
IEEE Trans. VLSI Syst., 2016

Area-Aware Decomposition for Single-Electron Transistor Arrays.
ACM Trans. Design Autom. Electr. Syst., 2016

Enabling New Computation Paradigms with HyperFET - An Emerging Device.
IEEE Trans. Multi-Scale Computing Systems, 2016

Towards a unified multiresolution vision model for autonomous ground robots.
Robotics Auton. Syst., 2016

Nonvolatile Processor Architectures: Efficient, Reliable Progress with Unstable Power.
IEEE Micro, 2016

Comparative Area and Parasitics Analysis in FinFET and Heterojunction Vertical TFET Standard Cells.
JETC, 2016

Enabling Internet-of-Things with Opportunities Brought by Emerging Devices, Circuits and Architectures.
Proceedings of the VLSI-SoC: System-on-Chip in the Nanoscale Era - Design, Verification and Reliability, 2016

Device Circuit Co Design of FEFET Based Logic for Low Voltage Processors.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

Ferroelectric Transistor based Non-Volatile Flip-Flop.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

LATTE: Low-power Audio Transform with TrueNorth Ecosystem.
Proceedings of the 2016 International Joint Conference on Neural Networks, 2016

Nonvolatile memory design based on ferroelectric FETs.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2015
Synthesis for Width Minimization in the Single-Electron Transistor Array.
IEEE Trans. VLSI Syst., 2015

Editorial.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2015

Nonvolatile Processor Architecture Exploration for Energy-Harvesting Applications.
IEEE Micro, 2015

Introduction to Special Issue on Neuromorphic Computing.
JETC, 2015

Thermal-Aware Application Scheduling on Device-Heterogeneous Embedded Architectures.
Proceedings of the 28th International Conference on VLSI Design, 2015

A High-Efficiency Switched-Capacitance HTFET Charge Pump for Low-Input-Voltage Applications.
Proceedings of the 28th International Conference on VLSI Design, 2015

Using Multiple-Input NEMS for Parallel A/D Conversion and Image Processing.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Comparing Energy, Area, Delay Tradeoffs in Going Vertical with CMOS and Asymmetric HTFETs.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Single-Ended and Differential MRAMs Based on Spin Hall Effect: A Layout-Aware Design Perspective.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Exploring memory controller configurations for many-core systems with 3D stacked DRAMs.
Proceedings of the Sixteenth International Symposium on Quality Electronic Design, 2015

Dynamic Machine Learning Based Matching of Nonvolatile Processor Microarchitecture to Harvested Energy Profile.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

Architecture exploration for ambient energy harvesting nonvolatile processors.
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

Exploring architectural heterogeneity in intelligent vision systems.
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015

A scalable architecture for multi-class visual object detection.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Visual co-occurrence network: using context for large-scale object recognition in retail.
Proceedings of the 13th IEEE Symposium on Embedded Systems For Real-time Multimedia, 2015

Platform-aware dynamic configuration support for efficient text processing on heterogeneous system.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Cognitive cameras: Assistive vision systems.
Proceedings of the 2015 International Conference on Compilers, 2015

A defect-aware approach for mapping reconfigurable Single-Electron Transistor arrays.
Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014
Accelerating Multiresolution Gabor Feature Extraction for Real Time Vision Applications.
Signal Processing Systems, 2014

Introduction to the Special Issue on Domain-Specific Multicore Computing.
ACM Trans. Embedded Comput. Syst., 2014

Optimizing the NoC Slack Through Voltage and Frequency Scaling in Hard Real-Time Embedded Systems.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

Editorial.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014

Tunnel FET technology: A reliability perspective.
Microelectron. Reliab., 2014

Tunnel FET RF Rectifier Design for Energy Harvesting Applications.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2014

Low-power high-speed current mode logic using Tunnel-FETs.
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014

Rf-powered systems using steep-slope devices.
Proceedings of the IEEE 12th International New Circuits and Systems Conference, 2014

Independently-Controlled-Gate FinFET 6T SRAM Cell Design for Leakage Current Reduction and Enhanced Read Access Speed.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

A Low-Voltage Low-Power LC Oscillator Using the Diode-Connected SymFET.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Computational Architectures Based on Coupled Oscillators.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Tunnel FET-based ultra-low power, low-noise amplifier design for bio-signal acquisition.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

An examination of the architecture and system-level tradeoffs of employing steep slope devices in 3D CMPs.
Proceedings of the ACM/IEEE 41st International Symposium on Computer Architecture, 2014

Exploiting natural redundancy in visual information.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

Refresh Enabled Video Analytics (REVA): Implications on power and performance of DRAM supported embedded visual systems.
Proceedings of the 32nd IEEE International Conference on Computer Design, 2014

A hardware accelerated multilevel visual classifier for embedded visual-assist systems.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

A task-oriented vision system.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

Data driven adaptation for QoS aware embedded vision systems.
Proceedings of the 2014 IEEE Global Conference on Signal and Information Processing, 2014

Modeling steep slope devices: From circuits to architectures.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Video analytics using beyond CMOS devices.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Width minimization in the Single-Electron Transistor array synthesis.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Steep Slope Devices: Enabling New Architectural Paradigms.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

2013
Hardware Acceleration for Neuromorphic Vision Algorithms.
Signal Processing Systems, 2013

Steep-Slope Devices: From Dark to Dim Silicon.
IEEE Micro, 2013

A Synthesis Algorithm for Reconfigurable Single-Electron Transistor Arrays.
JETC, 2013

Design of energy-efficient circuits and systems using tunnel field effect transistors.
IET Circuits, Devices & Systems, 2013

Keynote talk: Embedded vision systems.
Proceedings of the 26th International Conference on VLSI Design and 12th International Conference on Embedded Systems, 2013

Staggered latch bus: A reliable offset switched architecture for long on-chip interconnect.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

Saliency-driven dynamic configuration of HMAX for energy-efficient multi-object recognition.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2013

Evaluation of tunnel FET-based flip-flop designs for low power, high performance applications.
Proceedings of the International Symposium on Quality Electronic Design, 2013

EMERALD: Characterization of emerging applications and algorithms for low-power devices.
Proceedings of the 2012 IEEE International Symposium on Performance Analysis of Systems & Software, 2013

Tunnel FET-based ultra-low power, high-sensitivity UHF RFID rectifier.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

Steep switching tunnel FET: A promise to extend the energy efficient roadmap for post-CMOS digital and analog/RF applications.
Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013

Dynamic bandwidth adaptation using recognition accuracy prediction through pre-classification for embedded vision systems.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

A multi-resolution saliency framework to drive foveation.
Proceedings of the IEEE International Conference on Acoustics, 2013

TS-Router: On maximizing the Quality-of-Allocation in the On-Chip Network.
Proceedings of the 19th IEEE International Symposium on High Performance Computer Architecture, 2013

A Configurable Architecture for a Visual Saliency System and Its Application in Retail.
Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013

Saliency aware display power management.
Proceedings of the Design, Automation and Test in Europe, 2013

On reconfigurable single-electron transistor arrays synthesis using reordering techniques.
Proceedings of the Design, Automation and Test in Europe, 2013

Designing energy-efficient NoC for real-time embedded systems through slack optimization.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Run-time adaption for highly-complex multi-core systems.
Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2013

ShieldUS: A novel design of dynamic shielding for eliminating 3D TSV crosstalk coupling noise.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012
Targeted random test generation for power-aware multicore designs.
ACM Trans. Design Autom. Electr. Syst., 2012

Power Analysis Attack Resistance Engineering by Dynamic Voltage and Frequency Scaling.
ACM Trans. Embedded Comput. Syst., 2012

System-On-Chip for Biologically Inspired Vision Applications.
IPSJ Trans. System LSI Design Methodology, 2012

Multiresolution Gabor Feature Extraction for Real Time Applications.
Proceedings of the 2012 IEEE Workshop on Signal Processing Systems, 2012

Ultra Low Power Circuit Design Using Tunnel FETs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Design space exploration of workload-specific last-level caches.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Mitigating electromigration of power supply networks using bidirectional current stress.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012

Emulating Mammalian Vision on Reconfigurable Hardware.
Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012

Hazard driven test generation for SMT processors.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

An FPGA-based accelerator for cortical object classification.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Cache revive: architecting volatile STT-RAM caches for enhanced performance in CMPs.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Accelerating neuromorphic vision algorithms for recognition.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Performance enhancement under power constraints using heterogeneous CMOS-TFET multicores.
Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

When to forget: A system-level perspective on STT-RAMs.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

A reconfigurable accelerator for neuromorphic object recognition.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

A reconfigurable platform for the design and verification of domain-specific accelerators.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
Influence of Stacked 3D Memory/Cache Architectures on GPUs.
Proceedings of the 3D Integration for NoC-based SoC Architectures, 2011

FPGA Architecture for 2D Discrete Fourier Transform Based on 2D Decomposition for Large-sized Data.
Signal Processing Systems, 2011

Multidimensional DFT IP Generator for FPGA Platforms.
IEEE Trans. on Circuits and Systems, 2011

Variation-Aware Task and Communication Mapping for MPSoC Architecture.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2011

RAFT: A router architecture with frequency tuning for on-chip networks.
J. Parallel Distributed Comput., 2011

Exploiting Heterogeneity for Energy Efficiency in Chip Multiprocessors.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011

Guest Editorial Advances in Design of Energy-Efficient Circuits and Systems (Second Issue).
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011

A hardware architecture for accelerating neuromorphic vision algorithms.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2011

Variation-tolerant ultra low-power heterojunction tunnel FET SRAM design.
Proceedings of the 2011 IEEE/ACM International Symposium on Nanoscale Architectures, 2011

Towards Resilient Micro-architectures: Datapath Reliability Enhancement Using STT-MRAM.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

Impact of Circuit Degradation on FPGA Design Security.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

Improving energy efficiency of multi-threaded applications using heterogeneous CMOS-TFET multicores.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

A case for heterogeneous on-chip interconnects for CMPs.
Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011

Architecting on-chip interconnects for stacked 3D STT-RAM caches in CMPs.
Proceedings of the 38th International Symposium on Computer Architecture (ISCA 2011), 2011

A framework for accelerating neuromorphic-vision algorithms on FPGAs.
Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

Enabling architectural innovations using non-volatile memory.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

Exploring Gabor Filter Implementations for Visual Cortex Modeling on FPGA.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011

A streaming FPGA implementation of a steerable filter for real-time applications (abstract only).
Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

An FPGA Implementation of Information Theoretic Visual-Saliency System and Its Optimization.
Proceedings of the IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines, 2011

SHARC: A streaming model for FPGA accelerators and its application to Saliency.
Proceedings of the Design, Automation and Test in Europe, 2011

An energy-efficient heterogeneous CMP based on hybrid TFET-CMOS cores.
Proceedings of the 48th Design Automation Conference, 2011

An algorithm-architecture co-design framework for gridding reconstruction using FPGAs.
Proceedings of the 48th Design Automation Conference, 2011

Automated mapping for reconfigurable single-electron transistor arrays.
Proceedings of the 48th Design Automation Conference, 2011

Invited paper: Accelerating neuromorphic vision on FPGAs.
Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2011

FPGA-accelerator system for computing biologically inspired feature extraction models.
Proceedings of the Conference Record of the Forty Fifth Asilomar Conference on Signals, 2011

2010
Network-on-Chip Architectures - A Holistic Design Exploration
Lecture Notes in Electrical Engineering 45, Springer, ISBN: 978-90-481-3030-6, 2010

Total Power Optimization for Combinational Logic Using Genetic Algorithms.
Signal Processing Systems, 2010

On the Effects of Process Variation in Network-on-Chip Architectures.
IEEE Trans. Dependable Sec. Comput., 2010

Energy-Delay Performance of Nanoscale Transistors Exhibiting Single Electron Behavior and Associated Logic Circuits.
J. Low Power Electronics, 2010

Analyzing Energy-Delay Behavior in Room Temperature Single Electron Transistors.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

A Scalable Bandwidth Aware Architecture for Connected Component Labeling.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Bandwidth-intensive FPGA architecture for multi-dimensional DFT.
Proceedings of the IEEE International Conference on Acoustics, 2010

Thermal Gradient Aware Clock Skew Scheduling for FPGAs.
Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

Accelerating the Nonuniform Fast Fourier Transform Using FPGAs.
Proceedings of the 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2010

AutoFLEX: A Framework for Image Processing Applications on Multiple-FPGA Systems.
Proceedings of the 2010 International Conference on Engineering of Reconfigurable Systems & Algorithms, 2010

Investigating the impact of NBTI on different power saving cache strategies.
Proceedings of the Design, Automation and Test in Europe, 2010

A GPU based implementation of Center-Surround Distribution Distance for feature extraction and matching.
Proceedings of the Design, Automation and Test in Europe, 2010

Optimizing power and performance for reliable on-chip networks.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

A novel si-tunnel FET based SRAM design for ultra low-power 0.3V VDD applications.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2009
Compiler-assisted soft error detection under performance and energy constraints in embedded systems.
ACM Trans. Embedded Comput. Syst., 2009

Modeling Soft Errors at the Device and Logic Levels for Combinational Circuits.
IEEE Trans. Dependable Sec. Comput., 2009

Design of Thermally Robust Clock Trees Using Dynamically Adaptive Clock Buffers.
IEEE Trans. on Circuits and Systems, 2009

Process-Variation-Aware Adaptive Cache Architecture and Management.
IEEE Trans. Computers, 2009

An Automated Framework for Accelerating Numerical Algorithms on Reconfigurable Platforms Using Algorithmic/Architectural Optimization.
IEEE Trans. Computers, 2009

New-Age: A Negative Bias Temperature Instability-Estimation Framework for Microarchitectural Components.
International Journal of Parallel Programming, 2009

Clone Detection in Sensor Networks with Ad Hoc and Grid Topologies.
IJDSN, 2009

Predicting the performance and reliability of future field programmable gate arrays routing architectures with carbon nanotube bundle interconnect.
IET Circuits, Devices & Systems, 2009

Security and Dependability of Embedded Systems: A Computer Architects' Perspective.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

Ultra Low Energy Binary Decision Diagram Circuits Using Few Electron Transistors.
Proceedings of the Nano-Net - 4th International ICST Conference, 2009

Power and area reduction using carbon nanotube bundle interconnect in global clock tree distribution network.
Proceedings of the 2009 IEEE/ACM International Symposium on Nanoscale Architectures, 2009

Test Generation for Precise Interrupts on Out-of-Order Microprocessors.
Proceedings of the 10th International Workshop on Microprocessor Test and Verification, 2009

A case for dynamic frequency tuning in on-chip networks.
Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009

Lifetime Reliability Aware Design Flow Techniques for Dual-Vdd Based Platform FPGAs.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

A Novel Low Area Overhead Body Bias FPGA Architecture for Low Power Applications.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

Green transistors to green architectures.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs.
Proceedings of the 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 2009

In-Network Caching for Chip Multiprocessors.
Proceedings of the High Performance Embedded Architectures and Compilers, 2009

Exploiting clock skew scheduling for FPGA.
Proceedings of the Design, Automation and Test in Europe, 2009

A criticality-driven microarchitectural three dimensional (3D) floorplanner.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

A framework for estimating NBTI degradation of microarchitectural components.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

2008
Case Study of Reliability-Aware and Low-Power Design.
IEEE Trans. VLSI Syst., 2008

Design Space Exploration for 3-D Cache.
IEEE Trans. VLSI Syst., 2008

Designing a 3-D FPGA: Switch Box Architecture and Thermal Issues.
IEEE Trans. VLSI Syst., 2008

Toward Increasing FPGA Lifetime.
IEEE Trans. Dependable Sec. Comput., 2008

Exploring architectural solutions for energy optimisations in bus-based system-on-chip.
IET Computers & Digital Techniques, 2008

Efficient image reconstruction using partial 2D Fourier transform.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2008

Reconfigurable BDD based quantum circuits.
Proceedings of the 2008 IEEE International Symposium on Nanoscale Architectures, 2008

Hierarchical Soft Error Estimation Tool (HSEET).
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Impact of dynamic voltage and frequency scaling on the architectural vulnerability of GALS architectures.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

MIRA: A Multi-layered On-Chip Interconnect Router Architecture.
Proceedings of the 35th International Symposium on Computer Architecture (ISCA 2008), 2008

Comparative analysis of NBTI effects on low power and high performance flip-flops.
Proceedings of the 26th International Conference on Computer Design, 2008

Thermal-aware reliability analysis for platform FPGAs.
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008

Performance and power optimization through data compression in Network-on-Chip architectures.
Proceedings of the 14th International Conference on High-Performance Computer Architecture (HPCA-14 2008), 2008

A low-power phase change memory based hybrid cache architecture.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

A Hardware Efficient Support Vector Machine Architecture for FPGA.
Proceedings of the 16th IEEE International Symposium on Field-Programmable Custom Computing Machines, 2008

Analysis and solutions to issue queue process variation.
Proceedings of the 38th Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2008

Reliability-aware design for nanometer-scale devices.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
Reliability-aware Co-synthesis for Embedded Systems.
VLSI Signal Processing, 2007

On the Detection of Clones in Sensor Networks Using Random Key Predistribution.
IEEE Trans. Systems, Man, and Cybernetics, Part C, 2007

OS-Aware Branch Prediction: Improving Microprocessor Control Flow Prediction for Operating Systems.
IEEE Trans. Computers, 2007

Reducing non-deterministic loads in low-power caches via early cache set resolution.
Microprocessors and Microsystems, 2007

Design of power-aware FPGA fabrics.
IJES, 2007

On-chip bus thermal analysis and optimisation.
IET Computers & Digital Techniques, 2007

Optimising power efficiency in trace cache fetch unit.
IET Computers & Digital Techniques, 2007

Architecting Microprocessor Components in 3D Design Space.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Impact of NBTI on FPGAs.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Efficient Function Evaluations with Lookup Tables for Structured Matrix Operations.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

Investigating Simple Low Latency Reliable Multiported Register Files.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Impact of Process Variations on Carbon Nanotube Bundle Interconnect for Future FPGA Architectures.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Variation Impact on SER of Combinational Circuits.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Variation Analysis of CAM Cells.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Mitigating Thermal Effects on Clock Skew with Dynamically Adaptive Drivers.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

A novel dimensionally-decomposed router for on-chip communication in 3D architectures.
Proceedings of the 34th International Symposium on Computer Architecture (ISCA 2007), 2007

FPGA routing architecture analysis under variations.
Proceedings of the 25th International Conference on Computer Design, 2007

Variation-aware task allocation and scheduling for MPSoC.
Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Design of a Dynamic Priority-Based Fast Path Architecture for On-Chip Interconnects.
Proceedings of the 15th Annual IEEE Symposium on High-Performance Interconnects, 2007

TANOR: A Tool for Accelerating N-Body Simulations on Reconfigurable Platforms.
Proceedings of the FPL 2007, 2007

A Unified Streaming Architecture for Real Time Face Detection and Gender Classification.
Proceedings of the FPL 2007, 2007

Working with process variation aware caches.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Thermally robust clocking schemes for 3D integrated circuits.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Assessing carbon nanotube bundle interconnect for future FPGA architectures.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006
Block-based frequency scalable technique for efficient hierarchical coding.
IEEE Trans. Signal Processing, 2006

Reducing dynamic and leakage energy in VLIW architectures.
ACM Trans. Embedded Comput. Syst., 2006

An efficient architecture for motion estimation and compensation in the transform domain.
IEEE Trans. Circuits Syst. Video Techn., 2006

Inverse discrete cosine transform architecture exploiting sparseness and symmetry properties.
IEEE Trans. Circuits Syst. Video Techn., 2006

The Sleep Deprivation Attack in Sensor Networks: Analysis and Methods of Defense.
IJDSN, 2006

Reliability Concerns in Embedded System Designs.
IEEE Computer, 2006

A Hybrid SoC Interconnect with Dynamic TDMA-Based Transaction-Less Buses and On-Chip Networks.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

SEAT-LA: A Soft Error Analysis Tool for Combinational Logic.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

Performance Improvements through Timing Driven Reconfiguration of Black-Boxes in Platform FPGAs.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

Process Variation Aware Parallelization Strategies for MPSoCs.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

Geometric Tiling for Reducing Power Consumption in Structured Matrix Operations.
Proceedings of the 2006 IEEE International SOC Conference, Austin, Texas, USA, 2006

A Distributed Multi-Point Network Interface for Low-Latency, Deadlock-Free On-Chip Interconnects.
Proceedings of the 1st International ICST Conference on Nano-Networks, 2006

ViChaR: A Dynamic Virtual Channel Regulator for Network-on-Chip Routers.
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 2006

Compiler-directed thermal management for VLIW functional units.
Proceedings of the 2006 ACM SIGPLAN/SIGBED Conference on Languages, 2006

Reliability-Aware SOC Voltage Islands Partition and Floorplan.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

A Parallel Architecture for Hardware Face Detection.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Variation Aware Placement for FPGAs.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Delay and Energy Efficient Data Transmission for On-Chip Buses.
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Thermal Trends in Emerging Technologies.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Transaction Level Error Susceptibility Model for Bus Based SoC Architectures.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Interconnect and Thermal-aware Floorplanning for 3D Microprocessors.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Design and Management of 3D Chip Multiprocessors Using Network-in-Memory.
Proceedings of the 33rd International Symposium on Computer Architecture (ISCA 2006), 2006

A Gracefully Degrading and Energy-Efficient Modular Router Architecture for On-Chip Networks.
Proceedings of the 33rd International Symposium on Computer Architecture (ISCA 2006), 2006

Thermal characterization and optimization in platform FPGAs.
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Switch Box Architectures for Three-Dimensional FPGAs.
Proceedings of the 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 2006

Exploring Fault-Tolerant Network-on-Chip Architectures.
Proceedings of the 2006 International Conference on Dependable Systems and Networks (DSN 2006), 2006

On-chip bus thermal analysis and optimization.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Priority scheduling in digital microfluidics-based biochips.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

FLAW: FPGA lifetime awareness.
Proceedings of the 43rd Design Automation Conference, 2006

Object duplication for improving reliability.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

Leakage Optimized DECAP Design for FPGAs.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005
Soft errors issues in low-power caches.
IEEE Trans. VLSI Syst., 2005

Compiler-directed high-level energy estimation and optimization.
ACM Trans. Embedded Comput. Syst., 2005

Analyzing data reuse for cache reconfiguration.
ACM Trans. Embedded Comput. Syst., 2005

Power and Performance Analysis of Motion Estimation Based on Hardware and Software Realizations.
IEEE Trans. Computers, 2005

A Holistic Approach to Designing Energy-Efficient Cluster Interconnects.
IEEE Trans. Computers, 2005

An integer linear programming-based tool for wireless sensor networks.
J. Parallel Distributed Comput., 2005

Editorial.
JETC, 2005

Symmetric encryption in reconfigurable and custom hardware.
IJES, 2005

Improving Java performance using dynamic method migration on FPGAs.
IJES, 2005

Analysis of Error Recovery Schemes for Networks on Chips.
IEEE Design & Test of Computers, 2005

Networks on Chip (NoC): Interconnects of Next Generation Systems on Chip.
Advances in Computers, 2005

Accurate Stacking Effect Macro-Modeling of Leakage Power in Sub-100nm Circuits.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Influence of Leakage Reduction Techniques on Delay/Leakage Uncertainty.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Implementing LDPC Decoding on Network-on-Chip.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Detecting SEU-Caused Routing Errors in SRAM-Based FPGAs.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

A Nanosensor Array-Based VLSI Gas Discriminator.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

Simultaneous memory and bus partitioning for SoC architectures.
Proceedings of the Proceedings 2005 IEEE International SOC Conference, 2005

Soft errors: is the concern for soft-errors overblown?
Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

A Data-Driven Approach for Embedded Security.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

High Performance Array Processor for Video Decoding.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

Thermal-Aware Floorplanning Using Genetic Algorithms.
Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Online Detection and Diagnosis of Multiple Configuration Upsets in LUTs of SRAM-Based FPGAs.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005

Three-Dimensional Cache Design Exploration Using 3DCacti.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Temperature-Aware Voltage Islands Architecting in System-on-Chip Design.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Efficient methodology for detection and correction of SEU-based interconnect errors in FPGAs using partial reconfiguration (abstract only).
Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

Power Attack Resistant Cryptosystem Design: A Dynamic Voltage and Frequency Switching Approach.
Proceedings of the 2005 Design, 2005

Leakage-Aware Interconnect for On-Chip Network.
Proceedings of the 2005 Design, 2005

Simultaneous Partitioning and Frequency Assignment for On-Chip Bus Architectures.
Proceedings of the 2005 Design, 2005

Hotspot Prevention Through Runtime Reconfiguration in Network-On-Chip.
Proceedings of the 2005 Design, 2005

Thermal-Aware Task Allocation and Scheduling for Embedded Systems.
Proceedings of the 2005 Design, 2005

Compiler-Directed Instruction Duplication for Soft Error Detection.
Proceedings of the 2005 Design, 2005

A low latency router supporting adaptivity for on-chip interconnects.
Proceedings of the 42nd Design Automation Conference, 2005

Exploring technology alternatives for nano-scale FPGA interconnects.
Proceedings of the 42nd Design Automation Conference, 2005

A power estimation methodology for systemC transaction level models.
Proceedings of the 3rd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2005

Low-leakage robust SRAM cell design for sub-100nm technologies.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Designing reliable circuit in the presence of soft errors.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Leakage control in FPGA routing fabric.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Cluster-based detection of SEU-caused errors in LUTs of SRAM-based FPGAs.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Design and analysis of an NoC architecture from performance, reliability and energy perspective.
Proceedings of the 2005 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2005

2004
Data Organization and Retrieval on Parallel Air Channels: Performance and Energy Issues.
Wireless Networks, 2004

Instruction Scheduling for Low Power.
VLSI Signal Processing, 2004

Characterization and modeling of run-time techniques for leakage power reduction.
IEEE Trans. VLSI Syst., 2004

Guest Editorial.
IEEE Trans. VLSI Syst., 2004

Studying Energy Trade Offs in Offloading Computation/Compilation in Java-Enabled Mobile Devices.
IEEE Trans. Parallel Distrib. Syst., 2004

A compiler-based approach for dynamically managing scratch-pad memories in embedded systems.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2004

Reducing instruction cache energy consumption using a compiler-based strategy.
TACO, 2004

Optimizing Leakage Energy Consumption in Cache Bitlines.
Design Autom. for Emb. Sys., 2004

Embedded Hardware Face Detection.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

An Architecture for Motion Estimation in the Transform Domain.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

Designing Leakage Aware Multipliers.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

ChipPower: an architecture-level leakage simulator.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

A generic reconfigurable neural network architecture as a network on chip.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

Power-efficient implementation of turbo decoder in SDR system.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

Code protection for resource-constrained embedded devices.
Proceedings of the 2004 ACM SIGPLAN/SIGBED Conference on Languages, 2004

Field level analysis for heap space optimization in embedded java environments.
Proceedings of the 4th International Symposium on Memory Management, 2004

Evaluating Alternative Implementations for LDPC Decoder Check Node Function.
Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

Fault Tolerant Algorithms for Network-On-Chip Interconnect.
Proceedings of the 2004 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2004), 2004

The Effect of Threshold Voltages on the Soft Error Rate.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

Soft error and energy consumption interactions: a data cache perspective.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

A Parallel Architecture for Secure FPGA Symmetric Encryption.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

Search speed and power driven integrated software and hardware optimizations for motion estimation algorithms.
Proceedings of the 2004 IEEE International Conference on Multimedia and Expo, 2004

Thermal-Aware IP Virtualization and Placement for Networks-on-Chip Architecture.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

Improving soft-error tolerance of FPGA configuration bits.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Analyzing software influences on substrate noise: an ADC perspective.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Efficient VLSI implementation of inverse discrete cosine transform [image coding applications].
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004

Exploring Wakeup-Free Instruction Scheduling.
Proceedings of the 10th International Conference on High-Performance Computer Architecture (HPCA-10 2004), 2004

Design of a nanosensor array architecture.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004

A novel CLB architecture to detect and correct SEU in LUTs of SRAM-based FPGAs.
Proceedings of the 2004 IEEE International Conference on Field-Programmable Technology, 2004

A Dual-VDD Low Power FPGA Architecture.
Proceedings of the Field Programmable Logic and Application, 2004

Reducing leakage energy in FPGAs using region-constrained placement.
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

A Crosstalk Aware Interconnect with Variable Cycle Transmission.
Proceedings of the 2004 Design, 2004

Scheduling Reusable Instructions for Power Reduction.
Proceedings of the 2004 Design, 2004

Analyzing heap error behavior in embedded JVM environments.
Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2004

Reducing Energy Consumption in Chip Multiprocessors Using Workload Variations.
Proceedings of the Ultra Low-Power Electronics and Design, 2004

2003
Partitioned instruction cache architecture for energy efficiency.
ACM Trans. Embedded Comput. Syst., 2003

Evaluating Integrated Hardware-Software Optimizations Using a Unified Energy Estimation Framework.
IEEE Trans. Computers, 2003

Managing Leakage Energy in Cache Hierarchies.
J. Instruction-Level Parallelism, 2003

Leakage Current: Moore's Law Meets Static Power.
IEEE Computer, 2003

Analyzing Soft Errors in Leakage Optimized SRAM Design.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

Energy Efficient and Reliable System Design.
Proceedings of the IFIP VLSI-SoC 2003, 2003

Effect of Power Optimizations on Soft Error Rate.
Proceedings of the VLSI-SOC: From Systems to Chips, 2003

Heap compression for memory-constrained Java environments.
Proceedings of the 2003 ACM SIGPLAN Conference on Object-Oriented Programming Systems, 2003

The Sandbox Design Experience Course.
Proceedings of the 2003 International Conference on Microelectronics Systems Education, 2003

Adapting instruction level parallelism for optimizing leakage in VLIW architectures.
Proceedings of the 2003 Conference on Languages, 2003

Using Dynamic Branch Behavior for Power-Efficient Instruction Fetch.
Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

Interplay of energy and performance for disk arrays running transaction processing workloads.
Proceedings of the 2003 IEEE International Symposium on Performance Analysis of Systems and Software, 2003

Energy optimization techniques in cluster interconnects.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Estimating influence of data layout optimizations on SDRAM energy consumption.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

On load latency in low-power caches.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Exploiting program hotspots and code sequentiality for instruction cache leakage management.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Energy and Performance Considerations in Work Partitioning for Mobile Spatial Queries.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

Energy-Aware Compilation and Execution in Java-Enabled Mobile Devices.
Proceedings of the 17th International Parallel and Distributed Processing Symposium (IPDPS 2003), 2003

Computation and transmission energy modeling through profiling for MPEG4 video transmission.
Proceedings of the 2003 IEEE International Conference on Multimedia and Expo, 2003

Reducing dTLB Energy Through Dynamic Resizing.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003

Adapative Error Protection for Energy Efficiency.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

CCC: Crossbar Connected Caches for Reducing Energy Consumption of On-Chip Multiprocessors.
Proceedings of the 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), 2003

Compiler Support for Reducing Leakage Energy Consumption.
Proceedings of the 2003 Design, 2003

Masking the Energy Behavior of DES Encryption.
Proceedings of the 2003 Design, 2003

Implications of technology scaling on leakage reduction techniques.
Proceedings of the 40th Design Automation Conference, 2003

VL-CDRAM: variable line sized cached DRAMs.
Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003

Tracking object life cycle for leakage energy optimization.
Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, 2003

2002
Energy-performance trade-offs for spatial access methods on memory-resident data.
VLDB J., 2002

A clock power model to evaluate impact of architectural and technology optimizations.
IEEE Trans. VLSI Syst., 2002

Tuning garbage collection for reducing memory system energy in an embedded java environment.
ACM Trans. Embedded Comput. Syst., 2002

Using Memory Compression for Energy Reduction in an Embedded Java System.
Journal of Circuits, Systems, and Computers, 2002

Evaluating Run-Time Techniques for Leakage Power Reduction.
Proceedings of the ASPDAC 2002 / VLSI Design 2002, 2002

Compiler-Directed Array Interleaving for Reducing Energy in Multi-Bank Memories.
Proceedings of the ASPDAC 2002 / VLSI Design 2002, 2002

Compiler-directed instruction cache leakage optimization.
Proceedings of the 35th Annual International Symposium on Microarchitecture, 2002

Energy-conscious compilation based on voltage scaling.
Proceedings of the 2002 Joint Conference on Languages, 2002

Compiler-directed cache polymorphism.
Proceedings of the 2002 Joint Conference on Languages, 2002

Adaptive Garbage Collection for Battery-Operated Environments.
Proceedings of the 2nd Java Virtual Machine Research and Technology Symposium, 2002

Hardware-Software Co-Adaptation for Data-Intensive Embedded Applications.
Proceedings of the 2002 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002), 2002

Impact of Technology Scaling in the Clock System Power.
Proceedings of the 2002 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2002), 2002

Designing Energy-Efficient Software.
Proceedings of the 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 2002

Impact of Scaling on the Effectiveness of Dynamic Power Reduction Schemes.
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

Power efficient adaptive M-QAM design using adaptive pipelined analog-to-digital converter.
Proceedings of the IEEE International Conference on Acoustics, 2002

Using Complete Machine Simulation for Software Power Estimation: The SoftWatt Approach.
Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA'02), 2002

Tuning Garbage Collection in an Embedded Java Environment.
Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA'02), 2002

EAC: A Compiler Framework for High-Level Energy Estimation and Optimization.
Proceedings of the 2002 Design, 2002

Power-Efficient Trace Caches.
Proceedings of the 2002 Design, 2002

A Complete Phase-Locked Loop Power Consumption Model.
Proceedings of the 2002 Design, 2002

Scheduler-based DRAM energy management.
Proceedings of the 39th Design Automation Conference, 2002

Energy savings through compression in embedded Java environments.
Proceedings of the Tenth International Symposium on Hardware/Software Codesign, 2002

Understanding and improving operating system effects in control flow prediction.
Proceedings of the 10th International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-X), 2002

Leakage Energy Management in Cache Hierarchies.
Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques (PACT 2002), 2002

2001
Investigating Memory System Energy Behavior Using Software and Hardware Optimizations.
VLSI Design, 2001

Influence of compiler optimizations on system power.
IEEE Trans. VLSI Syst., 2001

Design considerations for databus charge recovery.
IEEE Trans. VLSI Syst., 2001

Java Runtime Systems: Characterization and Architectural Implications.
IEEE Trans. Computers, 2001

Hardware and Software Techniques for Controlling DRAM Power Modes.
IEEE Trans. Computers, 2001

Formulation and Validation of an Energy Dissipation Model for the Clock Generation Circuitry and Distribution Networks.
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Analyzing energy behavior of spatial access methods for memory-resident data.
Proceedings of the VLDB 2001, 2001

vEC: virtual energy counters.
Proceedings of the 2001 ACM SIGPLAN-SIGSOFT Workshop on Program Analysis For Software Tools and Engineering, 2001

SoC Design Skills: Collaboration Builds a Stronger SoC Design Team.
Proceedings of the 2001 International Conference on Microelectronics Systems Education, 2001

Exploiting VLIW schedule slacks for dynamic and leakage energy reduction.
Proceedings of the 34th Annual International Symposium on Microarchitecture, 2001

Morphable Cache Architectures: Potential Benefits.
Proceedings of The Workshop on Languages, 2001

Energy Behavior of Java Applications from the Memory Perspective.
Proceedings of the 1st Java Virtual Machine Research and Technology Symposium, 2001

Power-aware partitioned cache architectures.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

Influence of Array Allocation Mechanisms on Memory System Energy.
Proceedings of the 15th International Parallel & Distributed Processing Symposium (IPDPS-01), 2001

Use of Local Memory for Efficient Java Execution.
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

A Framework for Energy Estimation of VLIW Architecture.
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

DRAM Energy Management Using Software and Hardware Directed Power Mode Control.
Proceedings of the Seventh International Symposium on High-Performance Computer Architecture (HPCA'01), 2001

Dynamic Management of Scratch-Pad Memory Space.
Proceedings of the 38th Design Automation Conference, 2001

Energy-efficient instruction cache using page-based placement.
Proceedings of the 2001 International Conference on Compilers, 2001

2000
A Holistic Approach to System Level Energy Optimization.
Proceedings of the Integrated Circuit Design, 2000

Towards Energy-Aware Iteration Space Tiling.
Proceedings of the Languages, 2000

Experimental Evaluation of Energy Behavior of Iteration Space Tiling.
Proceedings of the Languages and Compilers for Parallel Computing, 2000

Memory system energy (poster session): influence of hardware-software optimizations.
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

Energy-driven integrated hardware-software optimizations using SimplePower.
Proceedings of the 27th International Symposium on Computer Architecture (ISCA 2000), 2000

Using complete system simulation to characterize SPECjvm98 benchmarks.
Proceedings of the 14th international conference on Supercomputing, 2000

Architectural Issues in Java Runtime Systems.
Proceedings of the Sixth International Symposium on High-Performance Computer Architecture, 2000

Energy-Aware Instruction Scheduling.
Proceedings of the High Performance Computing, 2000

Data Organization and Retrieval on Parallel Air Channels.
Proceedings of the High Performance Computing, 2000

A comparative study of power efficient SRAM designs.
Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000

The design and use of simplepower: a cycle-accurate energy estimation tool.
Proceedings of the 37th Conference on Design Automation, 2000

Energy-oriented compiler optimizations for partitioned memory architectures.
Proceedings of the 2000 International Conference on Compilers, 2000

1999
Energy Efficient Datapath Synthesis Using Dynamic Frequency Clocking and Multiple Voltages.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Tuning Branch Predictors to Support Virtual Method Invocation in Java.
Proceedings of the 5th USENIX Conference on Object-Oriented Technologies & Systems, 1999

1998
A linear array processor with dynamic frequency clocking for image processing applications.
IEEE Trans. Circuits Syst. Video Techn., 1998

Object-Oriented Architectural Support for a Java Processor.
Proceedings of the ECOOP'98, 1998

1996
SUBGEN: a genetic approach for subcircuit extraction.
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

A dynamic frequency linear array processor for image processing.
Proceedings of the 13th International Conference on Pattern Recognition, 1996

DFLAP: a dynamic frequency linear array processor.
Proceedings of the Proceedings 1996 International Conference on Image Processing, 1996

A VLSI array architecture with dynamic frequency clocking.
Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996


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