Pai-Tse Chiang

According to our database1, Pai-Tse Chiang authored at least 3 papers between 2013 and 2016.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of five.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2016
A QFHD 30-frames/s HEVC Decoder Design.
IEEE Trans. Circuits Syst. Video Technol., 2016

2013
Fast zero block detection and early CU termination for HEVC Video Coding.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A reconfigurable inverse transform architecture design for HEVC decoder.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013


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