Tian-Sheuan Chang

According to our database1, Tian-Sheuan Chang authored at least 131 papers between 1998 and 2024.

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Bibliography

2024
ACNPU: A 4.75TOPS/W 1080P@30FPS Super Resolution Accelerator With Decoupled Asymmetric Convolution.
IEEE Trans. Circuits Syst. I Regul. Pap., February, 2024

2023
Memory Bandwidth Efficient Design for Super-Resolution Accelerators With Structure Adaptive Fusion and Channel-Aware Addressing.
IEEE Trans. Very Large Scale Integr. Syst., June, 2023

A 1.6-mW Sparse Deep Learning Accelerator for Speech Separation.
IEEE Trans. Very Large Scale Integr. Syst., March, 2023

IQNet: Image Quality Assessment Guided Just Noticeable Difference Prefiltering For Versatile Video Coding.
CoRR, 2023

ASC: Adaptive Scale Feature Map Compression for Deep Neural Network.
CoRR, 2023

FPCIM: A Fully-Parallel Robust ReRAM CIM Processor for Edge AI Devices.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2022
A 14 μJ/Decision Keyword-Spotting Accelerator With In-SRAMComputing and On-Chip Learning for Customization.
IEEE Trans. Very Large Scale Integr. Syst., 2022

A Real-Time 1280 × 720 Object Detection Chip With 585 MB/s Memory Traffic.
IEEE Trans. Very Large Scale Integr. Syst., 2022

RangeSeg: Range-Aware Real Time Segmentation of 3D LiDAR Point Clouds.
IEEE Trans. Intell. Veh., 2022

Sparse Compressed Spiking Neural Network Accelerator for Object Detection.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Hardware-Robust In-RRAM-Computing for Object Detection.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2022

Deep Gait Tracking With Inertial Measurement Unit.
CoRR, 2022

A 14uJ/Decision Keyword Spotting Accelerator with In-SRAM-Computing and On Chip Learning for Customization.
CoRR, 2022

IMU Based Deep Stride Length Estimation With Self-Supervised Learning.
CoRR, 2022

A Real Time 1280x720 Object Detection Chip With 585MB/s Memory Traffic.
CoRR, 2022

An 1-bit by 1-bit High Parallelism In-RRAM Macro with Co-Training Mechanism for DCNN Applications.
Proceedings of the 2022 International Symposium on VLSI Design, Automation and Test, 2022

BSRA: Block-based Super Resolution Accelerator with Hardware Efficient Pixel Attention.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

PSCNN: A 885.86 TOPS/W Programmable SRAM-based Computing-In-Memory Processor for Keyword Spotting.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

A Real Time Super Resolution Accelerator with Tilted Layer Fusion.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

All Attention U-NET for Semantic Segmentation of Intracranial Hemorrhages In Head CT Images.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2022

Row-wise Accelerator for Vision Transformer.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022

2021
Pre-RTL DNN Hardware Evaluator With Fused Layer Support.
Proceedings of the 18th International SoC Design Conference, 2021

VSA: Reconfigurable Vectorwise Spiking Neural Network Accelerator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

A 48 TOPS and 20943 TOPS/W 512kb Computation-in-SRAM Macro for Highly Reconfigurable Ternary CNN Acceleration.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2021

2020
VWA: Hardware Efficient Vectorwise Accelerator for Convolutional Neural Network.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020

Image Synthesis With Efficient Defocus Blur for Stereoscopic Displays.
IEEE Access, 2020

Real-Time Wearable Gait Phase Segmentation for Running And Walking.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Zebra: Memory Bandwidth Reduction for CNN Accelerators with Zero Block Regularization of Activation Maps.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Efficient Accelerator for Dilated and Transposed Convolution with Decomposition.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

A Secure File Sharing System Based on IPFS and Blockchain.
Proceedings of the IECC 2020: 2nd International Electronics Communication Conference, 2020

Real Time On Sensor Gait Phase Detection with 0.5KB Deep Learning Model.
Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2020

2019
Run Time Adaptive Network Slimming for Mobile Environments.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

VSCNN: Convolution Neural Network Accelerator with Vector Sparsity.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

NV-BNN: An Accurate Deep Convolutional Neural Network Based on Binary STT-MRAM for Adaptive AI Edge.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
Data and Hardware Efficient Design for Convolutional Neural Network.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Mitigating Asymmetric Nonlinear Weight Update Effects in Hardware Neural Network Based on Analog Resistive Synapse.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

End-to-end hardware accelerator for deep convolutional neural network.
Proceedings of the 2018 International Symposium on VLSI Design, 2018

A Scoping Study on the Development of an Interactive Upper-Limb Rehabilitation System Framework for Patients with Stroke.
Proceedings of the Universal Access in Human-Computer Interaction. Virtual, Augmented, and Intelligent Environments, 2018

2017
Fast rate distortion optimization with adaptive context group modeling for HEVC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
A QFHD 30-frames/s HEVC Decoder Design.
IEEE Trans. Circuits Syst. Video Technol., 2016

Fast intra prediction algorithm and design for high efficiency video coding.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Perceptual oriented depth cue enhancement for stereoscopic view synthesis.
Proceedings of the True Vision - Capture, Transmission and Display of 3D Video, 2016

2015
Fast Motion Estimation Algorithm and Design for Real Time QFHD High Efficiency Video Coding.
IEEE Trans. Circuits Syst. Video Technol., 2015

A hardware-efficient deblocking filter design for HEVC.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Low complexity real time BCI for stroke rehabilitation.
Proceedings of the 2015 IEEE International Conference on Digital Signal Processing, 2015

Fast rate distortion optimization design for HEVC intra coding.
Proceedings of the 2015 IEEE International Conference on Digital Signal Processing, 2015

2014
Correction to "Low complexity formant estimation adaptive feedback cancellation for hearing aids using pitch based processing".
IEEE ACM Trans. Audio Speech Lang. Process., 2014

Low Complexity Formant Estimation Adaptive Feedback Cancellation for Hearing Aids Using Pitch Based Processing.
IEEE ACM Trans. Audio Speech Lang. Process., 2014

Analysis and implementation of low-power perceptual multiband noise reduction for the hearing aids application.
IET Circuits Devices Syst., 2014

Thermal-aware memory management unit of 3D-stacked DRAM for 3D high definition (HD) video.
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

Gradient-based PU size selection for HEVC intra prediction.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A real time 1080P 30FPS Gaussian Mixture Modeling design for background subtraction and object extraction.
Proceedings of the IEEE International Conference on Consumer Electronics - Taiwan, 2014

2013
135-MHz 258-K Gates VLSI Design for All-Intra H.264/AVC Scalable Video Encoder.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Algorithm and Architecture Design of Bandwidth-Oriented Motion Estimation for Real-Time Mobile Video Applications.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Fast SIFT Design for Real-Time Visual Feature Extraction.
IEEE Trans. Image Process., 2013

An Efficient Mode Preselection Algorithm for Fractional Motion Estimation in H.264/AVC Scalable Video Extension.
IEEE Trans. Circuits Syst. Video Technol., 2013

Fast prediction unit selection for HEVC fractional pel motion estimation design.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2013

Fast zero block detection and early CU termination for HEVC Video Coding.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A reconfigurable inverse transform architecture design for HEVC decoder.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Real-Time Disparity Estimation Engine for High-Definition 3 DTV Applications.
Proceedings of the Emerging Technologies for 3D Video: Creation, 2013

2012
Sub µW Noise Reduction for CIC Hearing Aids.
IEEE Trans. Very Large Scale Integr. Syst., 2012

A 385 MHz 13.54 K Gates Delay Balanced Two-Level CAVLC Decoder for Ultra HD H.264/AVC Video.
IEEE Trans. Circuits Syst. Video Technol., 2012

A Highly Efficient VLSI Architecture for H.264/AVC Level 5.1 CABAC Decoder.
IEEE Trans. Circuits Syst. Video Technol., 2012

A 135 MHz 542 k Gates High Throughput H.264/AVC Scalable High Profile Decoder.
IEEE Trans. Circuits Syst. Video Technol., 2012

A lossless embedded compression codec engine for HD video decoding.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

Fast disparity estimation for 3DTV applications.
Proceedings of the 2012 Visual Communications and Image Processing, 2012

A low complexity speech coder for binaural communication in hearing aids.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A high throughput CAVLC design for HEVC.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A low-power body-channel communication system for binaural hearing aids.
Proceedings of the 2012 IEEE Biomedical Circuits and Systems Conference, 2012

Fast intra prediction algorithm with transform domain edge detection for HEVC.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2011
A 124 Mpixels/s VLSI Design for Histogram-Based Joint Bilateral Filtering.
IEEE Trans. Image Process., 2011

VLSI Architecture for Real-Time HD1080p View Synthesis Engine.
IEEE Trans. Circuits Syst. Video Technol., 2011

Memory bandwidth-scalable motion estimation for mobile video coding.
EURASIP J. Adv. Signal Process., 2011

A 94fps view synthesis engine for HD1080p video.
Proceedings of the 2011 IEEE Visual Communications and Image Processing, 2011

Fast algorithm for local stereo matching in disparity estimation.
Proceedings of the 17th International Conference on Digital Signal Processing, 2011

An efficient mode pre-selection algorithm for H.264/AVC scalable video extension fractional motion estimation.
Proceedings of the 17th International Conference on Digital Signal Processing, 2011

Bandwidth-constrained motion estimation for real-time mobile video application.
Proceedings of the 17th International Conference on Digital Signal Processing, 2011

Real-time high-definition stereo matching on FPGA.
Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

2010
Architecture Design of Belief Propagation for Real-Time Disparity Estimation.
IEEE Trans. Circuits Syst. Video Technol., 2010

RD Optimized Bandwidth Efficient Motion Estimation and Its Hardware Design With On-Demand Data Access.
IEEE Trans. Circuits Syst. Video Technol., 2010

Algorithm and Architecture of Disparity Estimation With Mini-Census Adaptive Support Weight.
IEEE Trans. Circuits Syst. Video Technol., 2010

Fast stereo matching with predictive search range.
Proceedings of the Picture Coding Symposium, 2010

A high throughput VLSI design with hybrid memory architecture for H.264/AVC CABAC decoder.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Low memory cost bilateral filtering using stripe-based sliding integral histogram.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Stereoscopic images generation with directional Gaussian filter.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Efficient inter-layer prediction hardware design with extended spatial scalability for H.264/AVC scalable extension.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Perceptual multiband spectral subtraction for noise reduction in hearing aids.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2009
A 140-MHz 94 K Gates HD1080p 30-Frames/s Intra-Only Profile H.264 Encoder.
IEEE Trans. Circuits Syst. Video Technol., 2009

Analysis of shared-link AXI.
IET Comput. Digit. Tech., 2009

Low-memory Cost Belief Propagation Architecture for Disparity Estimation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

A Memory Efficient Fine Grain Scalability Coefficient Encoding Method for H.264/AVC Scalable Video Extension.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Memory Analysis for H.264/AVC Scalable Extension Encoder.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Bandwidth-rate-distortion optimized motion estimation.
Proceedings of the 2009 IEEE International Conference on Multimedia and Expo, 2009

2008
Adaptive De-Interlacing With Robust Overlapped Block Motion Compensation.
IEEE Trans. Circuits Syst. Video Technol., 2008

Architecture Design of Shape-Adaptive Discrete Cosine Transform and Its Inverse for MPEG-4 Video Coding.
IEEE Trans. Circuits Syst. Video Technol., 2008

A Hardware-Efficient H.264/AVC Motion-Estimation Design for High-Definition Video.
IEEE Trans. Circuits Syst. I Regul. Pap., 2008

A 242mW 10mm<sup>2</sup> 1080p H.264/AVC High-Profile Encoder Chip.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

Data reuse analysis of local stereo matching.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

ISID : In-order scan and indexed diffusion segmentation algorithm for stereo vision.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Block-based belief propagation with in-place message updating for stereo vision.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

Analysis of color space and similarity measure impact on stereo block matching.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007
A Fast Algorithm and Its VLSI Architecture for Fractional Motion Estimation for H.264/MPEG-4 AVC Video Coding.
IEEE Trans. Circuits Syst. Video Technol., 2007

Optimal Data Mapping for Motion Compensation in H.264 Video Decoding.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

Low Memory Cost Block-Based Belief Propagation for Stereo Correspondence.
Proceedings of the 2007 IEEE International Conference on Multimedia and Expo, 2007

Real-Time DSP Implementation on Local Stereo Matching.
Proceedings of the 2007 IEEE International Conference on Multimedia and Expo, 2007

PMRME: A Parallel Multi-Resolution Motion Estimation Algorithm and Architecture for HDTV Sized H.264 Video Coding.
Proceedings of the IEEE International Conference on Acoustics, 2007

A 61MHz 72K Gates 1280x720 30FPS H.264 Intra Encoder.
Proceedings of the IEEE International Conference on Acoustics, 2007

SIFME: A Single Iteration Fractional-Pel Motion Estimation Algorithm and Architecture for HDTV Sized H.264 Video Coding.
Proceedings of the IEEE International Conference on Acoustics, 2007

A Low Cost Context Adaptive Arithmetic Coder for H.264/MPEG-4 AVC Video Coding.
Proceedings of the IEEE International Conference on Acoustics, 2007

2006
An Efficient Binary Motion Estimation Algorithm and its Architecture for MPEG-4 Shape Encoding.
IEEE Trans. Circuits Syst. Video Technol., 2006

Fast Variable Block Size Motion Estimation by Adaptive Early Termination.
IEEE Trans. Circuits Syst. Video Technol., 2006

A High-Definition H.264/AVC Intra-Frame Codec IP for Digital Video and Still Camera Applications.
IEEE Trans. Circuits Syst. Video Technol., 2006

Combined Frame Memory Motion Compensation for Video Coding.
IEEE Trans. Circuits Syst. Video Technol., 2006

An in-place architecture for the deblocking filter in H.264/AVC.
IEEE Trans. Circuits Syst. II Express Briefs, 2006

A zero-skipping multi-symbol CAVLC decoder for MPEG-4 AVC/H.264.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A fast fractional pel motion estimation algorithm for H.264/MPEG-4 AVC.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A 1280×720 pixels 30 frames/s H.264/MPEG-4 AVC intra encoder.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Algorithms and DSP implementation of H.264/AVC.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

High Performance Context Adaptive Variable Length Coding Encoder for MPEG-4 AVC/H.264 Video Coding.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

A Fast Algorithm and Its Architecture for Motion Estimation in MPEG-4 AVC/H.264 Video Coding.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

A Memory Bandwidth Optimized Interpolator for Motion Compensation in the H.264 Video Decoding.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

A Display Order Oriented Scalable Video Decoder.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005
A memory-efficient realization of cyclic convolution and its application to discrete cosine transform.
IEEE Trans. Circuits Syst. Video Technol., 2005

The Long Length DHT Design with a New Hardware Efficient Distributed Arithmetic Approach and Cyclic Preserving Partitioning.
IEICE Trans. Electron., 2005

Fast three step intra prediction algorithm for 4×4 blocks in H.264.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Combined frame memory architecture for motion compensation in video decoding.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Fast block type decision algorithm for intra prediction in H.264 FRext.
Proceedings of the 2005 International Conference on Image Processing, 2005

A bandwidth efficient subsampling-based block matching architecture for motion estimation.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2002
On the data reuse and memory bandwidth analysis for full-search block-matching VLSI architecture.
IEEE Trans. Circuits Syst. Video Technol., 2002

2000
A simple processor core design for DCT/IDCT.
IEEE Trans. Circuits Syst. Video Technol., 2000

1998
Low power FIR filter realization with differential coefficients and input.
Proceedings of the 1998 IEEE International Conference on Acoustics, 1998


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