Parth Parekh

According to our database, Parth Parekh authored at least 16 papers between 2016 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2023

Bi-Directional Gated Ring Oscillator Time Integrator.

Fei Yuan, Parth Parekh, Yushi Zhou

IEEE Trans. Circuits Syst. I Regul. Pap., September, 2023

Underwater Robotics Semantic Parser Assistant.

Parth Parekh, Cedric McGuire, Jake Imyak

CoRR, 2023

2022

Improved Metastability of True Single-Phase Clock D-Flipflops With Applications in Vernier Time-to-Digital Converters.

Parth Parekh, Fei Yuan, Yushi Zhou

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Gated Vernier delay line time integrator with applications in ΔΣ time-to-digital converter.

Parth Parekh, Fei Yuan, Yushi Zhou

Microelectron. J., 2022

All-Digital Bi-Directional Gated Ring Oscillator Time Integrator for Mixed-Mode Signal Processing.

Parth Parekh, Fei Yuan, Yushi Zhou

Proceedings of the 20th IEEE Interregional NEWCAS Conference, 2022

Bi-Directional Gated Ring Oscillator Time Integrator for Time-Based Mixed-Signal Processing.

Parth Parekh, Fei Yuan, Yushi Zhou

Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022

2021

Gated Vernier Delay Line Time Integrator for Time-Mode Signal Processing.

Parth Parekh, Fei Yuan, Yushi Zhou

Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021

2020

Analysis and Design of an All-Digital ∆Σ TDC via Time-Mode Signal Processing.

Fei Yuan, Parth Parekh

IEEE Trans. Circuits Syst. II Express Briefs, 2020

Time-based all-digital Δ Σ time-to-digital converter with pre-skewed bi-directional gated delay line time integrator.

Fei Yuan, Parth Parekh

IET Circuits Devices Syst., 2020

All-Digital Time Integrator Using Bi-Directional Gated Vernier Delay Line.

Parth Parekh, Fei Yuan, Yushi Zhou

Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

Area/Power-Efficient True-Single-Phase-Clock D-Flipflops with Improved Metastability.

Parth Parekh, Fei Yuan, Yushi Zhou

Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

2019

All-Digital ∆Σ TDC with Current-Starved Bi-Directional Gated Delay Line Time Integrator.

Fei Yuan, Parth Parekh

Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

Time-Mode All-Digital Delta-Sigma Time-to-Digital Converter with Process Uncertainty Calibration.

Fei Yuan, Parth Parekh

Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

2018

All-digital ΔΣ time-to-digital converter with Bi-Directional gated delay line time integrator.

Young Jun Park, Parth Parekh, Fei Yuan

Microelectron. J., 2018

Power-Silicon Efficient All-Digital △Σ TDC with Differential Gated Delay Line Time Integrator.

Parth Parekh, Fei Yuan

Proceedings of the 16th IEEE International New Circuits and Systems Conference, 2018

2016

A Bayesian Ensemble for Unsupervised Anomaly Detection.

Edward Yu, Parth Parekh

CoRR, 2016