Pavankumarsharma Devulapalli

According to our database, Pavankumarsharma Devulapalli authored at least 1 paper in 2014.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of six.

2014

Power optimized PLL implementation in 180nm CMOS technology.

Sreehari Rao Patri, Pavankumarsharma Devulapalli, Dhananjay Kewale, Omkar Asbe, K. S. R. Krishna Prasad

Proceedings of the 18th International Symposium on VLSI Design and Test, 2014