Per Bjesse

According to our database, Per Bjesse authored at least 18 papers between 1998 and 2009.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2009

Word level bitwidth reduction for unbounded hardware model checking.

Per Bjesse

Formal Methods Syst. Des., 2009

2008

Word-Level Sequential Memory Abstraction for Model Checking.

Per Bjesse

Proceedings of the Formal Methods in Computer-Aided Design, 2008

A Practical Approach to Word Level Model Checking of Industrial Netlists.

Per Bjesse

Proceedings of the Computer Aided Verification, 20th International Conference, 2008

2007

A compositional approach to the combination of combinational and sequential equivalence checking of circuits without known reset states.

In-Ho Moon, Per Bjesse, Carl Pixley

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

2006

Practical Issues in Sequential Equivalence Checking through Alignability: Handling Don't Cares and Generating Debug Traces.

In-Ho Moon, Per Bjesse, Carl Pixley

Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006

2005

Automatic generalized phase abstraction for formal verification.

Per Bjesse, James H. Kukula

Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

2004

DAG-aware circuit compression for formal verification.

Per Bjesse, Arne Borälv

Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Using Counter Example Guided Abstraction Refinement to Find Complex Bugs.

Per Bjesse, James H. Kukula

Proceedings of the 2004 Design, 2004

2003

Design automation with mixtures of proof strategies for propositional logic.

Gunnar Andersson, Per Bjesse, Byron Cook, Ziyad Hanna

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Guiding SAT Diagnosis with Tree Decompositions.

Per Bjesse, James H. Kukula, Robert F. Damiano, Ted Stanion, Yunshan Zhu

Proceedings of the Theory and Applications of Satisfiability Testing, 2003

2002

Industrial Model Checking Based on Satisfiability Solvers.

Per Bjesse

Proceedings of the Model Checking of Software, 2002

A proof engine approach to solving combinational design automation problems.

Gunnar Andersson, Per Bjesse, Byron Cook, Ziyad Hanna

Proceedings of the 39th Design Automation Conference, 2002

2001

Gate Level Description of Synchronous Hardware and Automatic Verification Based on Theorem Proving.

Per Bjesse

PhD thesis, 2001

Finding Bugs in an Alpha Microprocessor Using Satisfiability Solvers.

Per Bjesse, Tim Leonard, Abdel Mokkedem

Proceedings of the Computer Aided Verification, 13th International Conference, 2001

2000

Symbolic Reachability Analysis Based on SAT-Solvers.

Parosh Aziz Abdulla, Per Bjesse, Niklas Eén

Proceedings of the Tools and Algorithms for Construction and Analysis of Systems, 2000

SAT-Based Verification without State Space Traversal.

Per Bjesse, Koen Claessen

Proceedings of the Formal Methods in Computer-Aided Design, Third International Conference, 2000

1999

Automatic Verification of Combinatorial and Pipelined FFT.

Per Bjesse

Proceedings of the Computer Aided Verification, 11th International Conference, 1999

1998

Lava: Hardware Design in Haskell.

Per Bjesse, Koen Claessen, Mary Sheeran, Satnam Singh

Proceedings of the third ACM SIGPLAN International Conference on Functional Programming (ICFP '98), 1998