Carl Pixley

According to our database1, Carl Pixley authored at least 50 papers between 1988 and 2009.

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Bibliography

2009
Solver technology for system-level to RTL equivalence checking.
Proceedings of the Design, Automation and Test in Europe, 2009

2008
Practical Considerations Concerning HL-to -RT Equivalence Checking.
Proceedings of the Hardware and Software: Verification and Testing, 2008

2007
A compositional approach to the combination of combinational and sequential equivalence checking of circuits without known reset states.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Memory Modeling in ESL-RTL Equivalence Checking.
Proceedings of the 44th Design Automation Conference, 2007

2006
Guest Editors' Introduction: The True State of the Art of ESL Design.
IEEE Des. Test Comput., 2006

Panel: Assertion-Based Verification -What's the Big Deal?
Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006

Practical Issues in Sequential Equivalence Checking through Alignability: Handling Don't Cares and Generating Debug Traces.
Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006

Constraint-based verification.
Springer, ISBN: 978-0-387-25947-5, 2006

2005
Constructing Efficient Formal Models from High-Level Descriptions Using Symbolic Simulation.
Int. J. Parallel Program., 2005

2004
Simplifying Boolean constraint solving for random simulation-vector generation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004

Guest Editors' Introduction: Exploring Synergies for Design Verification.
IEEE Des. Test Comput., 2004

Designers want proofs - but show me the money.
Proceedings of the 2nd ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2004), 2004

Non-miter-based Combinational Equivalence Checking by Comparing BDDs with Different Variable Orders.
Proceedings of the Formal Methods in Computer-Aided Design, 5th International Conference, 2004

2003
Sequential optimization in the absence of global reset.
ACM Trans. Design Autom. Electr. Syst., 2003

Panel Summaries.
IEEE Des. Test Comput., 2003

A Framework for Constrained Functional Verification.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

Constraint synthesis for environment modeling in functional verification.
Proceedings of the 40th Design Automation Conference, 2003

Formal verification - prove it or pitch it.
Proceedings of the 40th Design Automation Conference, 2003

2002
Simplifying Constraint Solving in Random Simulation Generation.
Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002

Simplifying Circuits for Formal Verification Using Parametric Representation.
Proceedings of the Formal Methods in Computer-Aided Design, 4th International Conference, 2002

2001
Theory of safe replacements for sequential circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Guest Editor's Introduction: Formal Verification of Commercial Integrated Circuits.
IEEE Des. Test Comput., 2001

Application of Formal Verification to Design Creation and Implementation.
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001

Experience with term level modeling and verification of the M*CORE <sup>TM</sup> microprocessor core.
Proceedings of the Sixth IEEE International High-Level Design Validation and Test Workshop 2001, 2001

2000
Automatic Vector Generation Using Constraints and Biasing.
J. Electron. Test., 2000

An Efficient Logic Equivalence Checker for Industrial Circuits.
J. Electron. Test., 2000

1999
Model Checking: A Hardware Design Perspective.
Int. J. Softw. Tools Technol. Transf., 1999

Integrated Formal and Informal Design Verification of Commercial Integrated Circuits.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1999

Modeling design constraints and biasing in simulation using BDDs.
Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

1998
Approximate reachability don't cares for CTL model checking.
Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Design Constraints in Symbolic Model Checking.
Proceedings of the Computer Aided Verification, 10th International Conference, 1998

Logic and Functional Verification in a Commercial Semiconductor Environment.
Proceedings of the 1st International Conference on Application of Concurrency to System Design (ACSD '98), 1998

1997
Intertwined Development and Formal Verification of a 60x Bus Model.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

Formal Verification of FIRE: A Case Study.
Proceedings of the 34st Conference on Design Automation, 1997

1996
Commercial Design Verification: Methodology and Tools.
Proceedings of the Proceedings IEEE International Test Conference 1996, 1996

1995
Power-Up Delay for Retiming Digital Circuits.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995

Exploiting power-up delay for sequential optimization.
Proceedings of the Proceedings EURO-DAC'95, 1995

The Validity of Retiming Sequential Circuits.
Proceedings of the 32st Conference on Design Automation, 1995

1994
Exact calculation of synchronizing sequences based on binary decision diagrams.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1994

Multi-level synthesis for safe replaceability.
Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

The Verifiacation Problem for Safe Replaceability.
Proceedings of the Computer Aided Verification, 6th International Conference, 1994

1993
Synchronizing sequences and symbolic traversal techniques in test generation.
J. Electron. Test., 1993

Minimum Length Synchronizing Sequences of Finite State Machine.
Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992
A theory and implementation of sequential hardware equivalence.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

Exact Calculation of Synchronization Sequences Based on Binary Decision Diagrams.
Proceedings of the 29th Design Automation Conference, 1992

1991
Automatic Derivation of FSM Specification to Implementation Encoding.
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991

Calculating Resetability and Reset Sequences.
Proceedings of the 1991 IEEE/ACM International Conference on Computer-Aided Design, 1991

1990
A Computation Theory and Implementation of Sequential Hardware Equivalence.
Proceedings of the Computer-Aided Verification, 1990

Introduction to a Computational Theory and Implementation of Sequential Hardware Equivalence.
Proceedings of the Computer Aided Verification, 2nd International Workshop, 1990

1988
An Incremental Garbage Collection Algorithm for Multi-Mutator Systems.
Distributed Comput., 1988


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