Peter M. Kelly

According to our database1, Peter M. Kelly authored at least 26 papers between 1977 and 2011.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2011
On Two-Layer Brain-Inspired Hierarchical Topologies - A Rent's Rule Approach -.
Trans. High Perform. Embed. Archit. Compil., 2011

Evaluating the training dynamics of a CMOS based synapse.
Proceedings of the 2011 International Joint Conference on Neural Networks, 2011

2009
Lambda calculus as a workflow model.
Concurr. Comput. Pract. Exp., 2009

Reduced Interconnects in Neural Networks Using a Time Multiplexed Architecture Based on Quantum Devices.
Proceedings of the Nano-Net - 4th International ICST Conference, 2009

On Two-Layer Hierarchical Networks How Does the Brain Do This?
Proceedings of the Nano-Net - 4th International ICST Conference, 2009

2008
A Solid-State Neuron for Spiking Neural Network Implementation.
Eng. Lett., 2008

On brain-inspired connectivity and hybrid network topologies.
Proceedings of the 2008 IEEE International Symposium on Nanoscale Architectures, 2008

A programmable facilitating synapse device.
Proceedings of the International Joint Conference on Neural Networks, 2008

A time multiplexed architecture for neural networks using quantum devices.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

2007
Inter-neuron communication strategies for spiking neural networks.
Neurocomputing, 2007

Analog Spiking Neuron with Charge-Coupled Synapses.
Proceedings of the World Congress on Engineering, 2007

A Distributed Virtual Machine for Parallel Graph Reduction.
Proceedings of the Eighth International Conference on Parallel and Distributed Computing, 2007

A Biologically Plausible Neuron Circuit.
Proceedings of the International Joint Conference on Neural Networks, 2007

2006
A Silicon Synapse Based on a Charge Transfer Device for Spiking Neural Network Application.
Proceedings of the Advances in Neural Networks - ISNN 2006, Third International Symposium on Neural Networks, Chengdu, China, May 28, 2006

Inter-Neuron Communications for Large-Scale Neural Networks using Capacitive Coupling.
Proceedings of the International Joint Conference on Neural Networks, 2006

On the Design of a Low Power Compact Spiking Neuron Cell Based on Charge-Coupled Synapses.
Proceedings of the International Joint Conference on Neural Networks, 2006

A Time Multiplexing Architecture for Inter-neuron Communications.
Proceedings of the Artificial Neural Networks, 2006

Compilation of XSLT into Dataflow Graphs for Web Service Composition.
Proceedings of the Sixth IEEE International Symposium on Cluster Computing and the Grid (CCGrid 2006), 2006

A simplified approach to web service development.
Proceedings of the proceedings of the Fourth Australasian Symposium on Grid Computing and e-Research (AusGrid 2006) and the Fourth Australasian Information Security Workshop (Network Security) (AISW 2006), 2006

2005
A Quaternary CLB Design Using Quantum Device Technology on Silicon for FPGA Neural Network Architectures.
Proceedings of the Computational Intelligence and Bioinspired Systems, 2005

Distributed, Parallel Web Service Orchestration Using XSLT.
Proceedings of the First International Conference on e-Science and Grid Technologies (e-Science 2005), 2005

Reducing Interconnection Resource Overhead in Nano-scale FPGAs through MVL Signal Systems.
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

2003
Re-Programmable MVL Circuits and Architecture to Enable Evolvable MVL Hardware.
J. Multiple Valued Log. Soft Comput., 2003

A Binary Multiplier Using RTD Based Threshold Logic Gates.
Proceedings of the Artificial Neural Nets Problem Solving Methods, 2003

2002
Investigation of a programmable threshold logic gate array.
Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

1977
Implementing Spread Spectrum Technology in the Land Mobile Radio Services.
IEEE Trans. Commun., 1977


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