Valeriu Beiu

According to our database1, Valeriu Beiu authored at least 74 papers between 1988 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Bibliography

2020
Studying the Binary Erasure Polarization Subchannels Using Network Reliability.
IEEE Commun. Lett., 2020

Tight Bounds on the Coeffcients of Consecutive k-out-of-n: F Systems.
CoRR, 2020

Why Reliability for Computing Needs Rethinking.
Proceedings of the International Conference on Rebooting Computing, 2020

2019
Fast Reliability Ranking of Matchstick Minimal Networks.
CoRR, 2019

2018
How Reliable are Compositions of Series and Parallel Networks Compared with Hammocks?
Int. J. Comput. Commun. Control, 2018

On the Exact Reliability Enhancements of Small Hammock Networks.
IEEE Access, 2018

Vulnerabilities of the McEliece Variants Based on Polar Codes.
Proceedings of the Innovative Security Solutions for Information Technology and Communications, 2018

2017
On hammock networks - sixty years after.
Proceedings of the 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2017

2015
Lower and Upper Reliability Bounds for Consecutive-k-Out-of-n: F Systems.
IEEE Trans. Reliab., 2015

Reliability bounds for two dimensional consecutive systems.
Nano Commun. Networks, 2015

Statistical analysis of static noise margins.
Proceedings of the European Conference on Circuit Theory and Design, 2015

Reliability schemes for nano-communications.
Proceedings of the European Conference on Circuit Theory and Design, 2015

2014
Enhancing the Static Noise Margins by Upsizing Length for Ultra-Low Voltage/Power/Energy Gates.
J. Low Power Electron., 2014

Why hybridize NEMS with CMOS?
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

Deciphering the Reliability Scheme of the Neurons - One Ion Channel at a Time.
Proceedings of the 8th International Conference on Bio-inspired Information and Communications Technologies, 2014

2013
Enabling sizing for enhancing the static noise margins.
Proceedings of the International Symposium on Quality Electronic Design, 2013

Using body bias when upsizing length for maximizing the static noise margins of CMOS gates.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

On Schmitt trigger and other inverters.
Proceedings of the 20th IEEE International Conference on Electronics, 2013

2012
Optimum Reliability Sizing for Complementary Metal Oxide Semiconductor Gates.
IEEE Trans. Reliab., 2012

GREDA: A Fast and More Accurate Gate Reliability EDA Tool.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2012

A Mathematical Model for the Analysis of the Johnson-Nyquist Thermal Noise on the Reliability in Nano-Communications.
Proceedings of the Bio-Inspired Models of Network, Information, and Computing Systems, 2012

2011
Using Bayesian Networks to Accurately Calculate the Reliability of Complementary Metal Oxide Semiconductor Gates.
IEEE Trans. Reliab., 2011

On Two-Layer Brain-Inspired Hierarchical Topologies - A Rent's Rule Approach -.
Trans. High Perform. Embed. Archit. Compil., 2011

Exploring retrograde signaling via astrocytes as a mechanism for self repair.
Proceedings of the 2011 International Joint Conference on Neural Networks, 2011

On axon-inspired communications.
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011

2010
On NOR-2 von Neumann multiplexing.
Proceedings of the 5th International Design and Test Workshop, 2010

A Position-Based Broadcast Relay Approach in Mobile Vehicle-to-Vehicle Network.
Proceedings of the 2010 International Conference on Wireless Networks, 2010

2009
Device-Level Majority von Neumann Multiplexing.
Proceedings of the Encyclopedia of Artificial Intelligence (3 Volumes), 2009

Reduced Interconnects in Neural Networks Using a Time Multiplexed Architecture Based on Quantum Devices.
Proceedings of the Nano-Net - 4th International ICST Conference, 2009

A Bayesian-Based EDA Tool for Nano-circuits Reliability Calculations.
Proceedings of the Nano-Net - 4th International ICST Conference, 2009

On Two-Layer Hierarchical Networks How Does the Brain Do This?
Proceedings of the Nano-Net - 4th International ICST Conference, 2009

On Wires Holding a Handful of Electrons.
Proceedings of the Nano-Net - 4th International ICST Conference, 2009

2008
On brain-inspired hybrid topologies for nano-architectures - a Rent's rule approach -.
Proceedings of the 2008 International Conference on Embedded Computer Systems: Architectures, 2008

On brain-inspired connectivity and hybrid network topologies.
Proceedings of the 2008 IEEE International Symposium on Nanoscale Architectures, 2008

Does the brain really outperform Rent's rule?
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007
Serial Addition: Locally Connected Architectures.
IEEE Trans. Circuits Syst. I Regul. Pap., 2007

What von Neumann Did Not Say About Multiplexing Beyond Gate Failures - The Gory Details.
Proceedings of the Computational and Ambient Intelligence, 2007

Grand Challenges of Nanoelectronics and Possible Architectural Solutions: What Do Shannon, von Neumann, Kolmogorov, and Feynman Have to do with Moore.
Proceedings of the 37th International Symposium on Multiple-Valued Logic, 2007

Long Live Small Fan-in Majority Gates Their Reign Looks Like Coming!
Proceedings of the IEEE International Conference on Application-Specific Systems, 2007

2006
Gate Failures Effectively Shape Multiplexing.
Proceedings of the 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 2006

Multiplexing Schemes in Single-Electron Technology.
Proceedings of the 2006 IEEE/ACS International Conference on Computer Systems and Applications (AICCSA 2006), 2006

Femto Joule Switching for Nano Electronics.
Proceedings of the 2006 IEEE/ACS International Conference on Computer Systems and Applications (AICCSA 2006), 2006

2005
Using Kolmogorov Inspired Gates for Low Power Nanoelectronics.
Proceedings of the Computational Intelligence and Bioinspired Systems, 2005

Ultra Low-Power Neural Inspired Addition: When Serial Might Outperform Parallel Architectures.
Proceedings of the Computational Intelligence and Bioinspired Systems, 2005

On the Advantages of Serial Architectures for Low-Power Reliable Computations.
Proceedings of the 16th IEEE International Conference on Application-Specific Systems, 2005

2004
Characterization of a 16-bit threshold logic single-electron technology adder.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A Novel Segmented Parabolic Sine Approximation for Direct Digital Frequency Synthesizers.
Proceedings of the International Conference on Embedded Systems and Applications, 2004

Optimal Practical Perceptron Addition Application to Single Electron Technology.
Proceedings of the International Conference on Embedded Systems and Applications, 2004

A Novel Highly Reliable Low-Power Nano Architecture When von Neumann Augments.
Proceedings of the 15th IEEE International Conference on Application-Specific Systems, 2004

2003
VLSI implementations of threshold logic-a comprehensive survey.
IEEE Trans. Neural Networks, 2003

Review of Differential Threshold Gate Implementations.
Proceedings of the IASTED International Conference on Neural Networks and Computational Intelligence, 2003

On Existential and Constructive Neural Complexity Results.
Proceedings of the IASTED International Conference on Neural Networks and Computational Intelligence, 2003

A Modified Fuzzy ARTMAP Architecture for Incremental Learning Function Approximation.
Proceedings of the IASTED International Conference on Neural Networks and Computational Intelligence, 2003

Split-Precharge Differential Noise-Immune Threshold Logic Gate (SPD-NTL).
Proceedings of the Artificial Neural Nets Problem Solving Methods, 2003

Review of Capacitive Threshold Gate Implementations.
Proceedings of the Artificial Neural Networks and Neural Information Processing, 2003

Constructive Threshold Logic Addition A Synopsis of the Last Decade.
Proceedings of the Artificial Neural Networks and Neural Information Processing, 2003

1999
A Constructive Approach to Calculating Lower Entropy Bounds.
Neural Process. Lett., 1999

Neural Addition and Fibonacci Numbers.
Proceedings of the Engineering Applications of Bio-Inspired Artificial Neural Networks, 1999

1998
Deeper Sparsely Nets can be Optimal.
Neural Process. Lett., 1998

On the circuit and VLSI complexity of threshold gate COMPARISON.
Neurocomputing, 1998

On Kolmogorov's Superpositions and Boolean Functions.
Proceedings of the 5th Brazilian Symposium on Neural Networks (SBRN '98), 1998

2D Neural Hardware versus 3D Biological Ones.
Proceedings of the International ICSC / IFAC Symposium on Neural Computation (NC 1998), 1998

Implementing size-optimal discrete neural networks require analog circuitry.
Proceedings of the 9th European Signal Processing Conference, 1998

1997
On limited fan-in optimal neural networks.
Proceedings of the 4th Brazilian Symposium on Neural Networks, 1997

Tight Bounds on the Size of Neural Networks for Classification Problems.
Proceedings of the Biological and Artificial Computation: From Neuroscience to Technology, 1997

Enhanced lower entropy bounds with application to constructive learning.
Proceedings of the 23rd EUROMICRO Conference '97, 1997

1996
On the Circuit Complexity of Sigmoid Feedforward Neural Networks.
Neural Networks, 1996

1995
Density Estimation as a Preprocessing Step for Constructive Algorithms.
Proceedings of the Neural Networks: Artificial Intelligence and Industrial Applications, 1995

Optimal Mapping of Neural Networks onto FPGA's - A New Constructive Algorithm -.
Proceedings of the From Natural to Artificial Neural Computation, 1995

VLSI Optimal Neural Network Learning Algorithm.
Proceedings of the Artificial Neural Nets and Genetic Algorithms, 1995

1994
Closse Approximations of Sigmoid Functions by Sum of Step for VLSI Implementation of Neural Networks.
Sci. Ann. Cuza Univ., 1994

VLSI complexity reduction by piece-wise approximation of the sigmoid function.
Proceedings of the ESANN 1994, 1994

1993
Efficient decomposition of comparison and its applications.
Proceedings of the ESANN 1993, 1993

1988
VLSI arrays implementing parallel line-drawing algorithms.
Proceedings of the Parcella '88, 1988


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