Peter Rössler

Orcid: 0000-0002-0557-229X

According to our database1, Peter Rössler authored at least 22 papers between 2000 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2023
Open-Source Ethernet MAC IP Cores for FPGAs: Overview and Evaluation.
Int. J. Reconfigurable Comput., 2023

2020
Programmable logic devices - key components for today's and tomorrow's electronic-based systems.
Elektrotech. Informationstechnik, 2020

Forschung an österreichischen Fachhochschulen.
Elektrotech. Informationstechnik, 2020

Evaluation of Open-Source Linear Algebra Libraries targeting ARM and RISC-V Architectures.
Proceedings of the 2020 Federated Conference on Computer Science and Information Systems, 2020

2019
FIJI: Fault InJection Instrumenter.
EURASIP J. Embed. Syst., 2019

Open-Source RISC-V Processor IP Cores for FPGAs - Overview and Evaluation.
Proceedings of the 8th Mediterranean Conference on Embedded Computing, 2019

Evaluation of Open-Source Linear Algebra Libraries in Embedded Applications.
Proceedings of the 8th Mediterranean Conference on Embedded Computing, 2019

2018
Preliminary Evaluation of High-level Synthesis Tools - Xilinx Vivado and PandA Bambu.
Proceedings of the 13th IEEE International Symposium on Industrial Embedded Systems, 2018

A Model Railway based Demonstrator for Saftey-Critical Systems.
Proceedings of the 12th European Workshop on Microelectronics Education, 2018

2015
Digitale Mikroelektronik in Österreich.
Elektrotech. Informationstechnik, 2015

A netlist-level fault-injection tool for FPGAs.
Elektrotech. Informationstechnik, 2015

Logic synthesis of assertions for saftey-critical applications.
Proceedings of the IEEE International Conference on Industrial Technology, 2015

2014
Considerations on teaching digital ASIC design.
Proceedings of the 10th IEEE/ASME International Conference on Mechatronic and Embedded Systems and Applications, 2014

2013
A low-cost sound generator for an electric quad bike.
Proceedings of the 2nd Mediterranean Conference on Embedded Computing, 2013

2010
Eine neuartige Lösung für Test und Debugging in vernetzten eingebetteten Systemen.
Elektrotech. Informationstechnik, 2010

2009
Evaluation of an Esterel-based hardware/software co-design flow.
Proceedings of the IEEE Fourth International Symposium on Industrial Embedded Systems, 2009

2008
Development of a flexible gateway platform for automotive networks.
Proceedings of 13th IEEE International Conference on Emerging Technologies and Factory Automation, 2008

2007
Design Considerations for Scalable High-Performance Vision Systems Embedded in Industrial Print Inspection Machines.
EURASIP J. Embed. Syst., 2007

Performance Benchmark of DSP and FPGA Implementations of Low-Level Vision Algorithms.
Proceedings of the 2007 IEEE Computer Society Conference on Computer Vision and Pattern Recognition (CVPR 2007), 2007

2006
Architecture for hardware driven image inspection based on FPGAs.
Proceedings of the Real-Time Image Processing 2006, San Jose, CA, USA, January 15, 2006, 2006

2002
A Hard Real-Time Bus Arbitration Protocol based on EIA-709.
Proceedings of the 14th Euromicro Conference on Real-Time Systems (ECRTS 2002), 2002

2000
Feldbusse für die Heim- und Gebäudeautomation (Fieldbus Systems for Home- and Building Automation).
Informationstechnik Tech. Inform., 2000


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