Pinfeng Jiang
Orcid: 0009-0002-3242-1574
According to our database1,
Pinfeng Jiang authored at least 4 papers
in 2025.
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Bibliography
2025
ISARA: An Island-Style Systolic Array Reconfigurable Accelerator Based on Memristors for Deep Neural Networks.
IEEE Trans. Very Large Scale Integr. Syst., April, 2025
Optimizing hardware-software co-design based on non-ideality in memristor crossbars for in-memory computing.
Sci. China Inf. Sci., 2025
ReBA: A Hybrid Sparse Reconfigurable Butterfly Accelerator for Solving Partial Differential Equations via Hardware and Algorithm Co-Design.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2025
SPARTA: Spike-Aware Token Skipping Co-Optimization with Heterogeneous ReRAM-CIM Architecture for Spiking Transformer Acceleration.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2025