Piotr R. Sidorowicz

According to our database1, Piotr R. Sidorowicz authored at least 3 papers between 1998 and 2002.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

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Bibliography

2002
A framework for testing special-purpose memories.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

1999
Modeling and Testing Transistor Faults in Content-Addressable Memories.
Proceedings of the 7th IEEE International Workshop on Memory Technology, 1999

1998
An Approach to Modeling and Testing Memories and Its Application to CAMs.
Proceedings of the 16th IEEE VLSI Test Symposium (VTS '98), 28 April, 1998


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