Po-Yu Yeh

According to our database, Po-Yu Yeh authored at least 4 papers between 2009 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2025

23.5 MAE: A 3nm 0.168mm² 576MAC Mini AutoEncoder with Line-Based Depth-First Scheduling for Generative AI in Vision on Edge Devices.

Shih-Wei Hsieh, Chia-Hung Yuan, Ming-Hung Lin, Ping-Yuan Tsai, You-Yu Nian, Chia-Yuan Cheng, Hung-Wei Chih, Po-Han Chiang, Ming-Hsuan Chiang, Yuan-Jung Kuo, Yu-Wei Wu, Yi-Syuan Chen, Po-Heng Chen, Sandy Huang, Ming-En Shih, Chia-Ping Chen, Abrams Chen, Shen-Kai Chang, Chih-Ming Wang, Po-Yu Yeh, Jett Liu, Yung-Chang Chang, Chung-Yi Chen, Chi-Cheng Ju, Chi-Hui Wang, Yucheun Kevin Jou

Proceedings of the IEEE International Solid-State Circuits Conference, 2025

2010

Effective design-for-testability techniques for H.264 all-binary integer motion estimation.

Po-Yu Yeh, Bo-Yuan Ye, Sy-Yen Kuo, Ing-Yi Chen

IET Circuits Devices Syst., 2010

2009

Design-for-testability techniques for CORDIC design.

Bo-Yuan Ye, Po-Yu Yeh, Sy-Yen Kuo, Ing-Yi Chen

Microelectron. J., 2009

Scalable and bijective cells for C-testable iterative logic array architectures.

Bo-Yuan Ye, Po-Yu Yeh, Sy-Yen Kuo, Ing-Yi Chen

IET Circuits Devices Syst., 2009