Po-Yu Yeh

According to our database1, Po-Yu Yeh authored at least 6 papers between 2009 and 2026.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
MADiC: A 3nm 7.4TOPS/mm<sup>2</sup>, 17.4TOPS/W Generative Diffusion Accelerator Enabled by Hardware-Compiler Co-Optimization of Memory Hierarchy and Operator Parallelism.
Proceedings of the IEEE International Solid-State Circuits Conference, 2026

2025
23.5 MAE: A 3nm 0.168mm<sup>2</sup> 576MAC Mini AutoEncoder with Line-Based Depth-First Scheduling for Generative AI in Vision on Edge Devices.
Proceedings of the IEEE International Solid-State Circuits Conference, 2025

Message-Passing Algorithm for Pseudoinverse Computation in Graph-Based Decoding of Noisy IRSA.
Proceedings of the 2025 IEEE Global Communications Conference, 2025

2010
Effective design-for-testability techniques for H.264 all-binary integer motion estimation.
IET Circuits Devices Syst., 2010

2009
Design-for-testability techniques for CORDIC design.
Microelectron. J., 2009

Scalable and bijective cells for C-testable iterative logic array architectures.
IET Circuits Devices Syst., 2009


  Loading...