Pooneh Safayenikoo
Orcid: 0000-0002-4654-8667
According to our database1,
Pooneh Safayenikoo
authored at least 9 papers
between 2016 and 2023.
Collaborative distances:
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Bibliography
2023
CoRR, 2023
2022
Energy-efficient Non Uniform Last Level Caches for Chip-multiprocessors Based on Compression.
CoRR, 2022
2021
IEEE J. Emerg. Sel. Topics Circuits Syst., 2021
2018
NIZCache: Energy-efficient Non-uniform Cache Architecture for Chip-multiprocessors Based on Invalid and Zero Lines.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
An Energy-Efficient Cache Architecture for Chip-Multiprocessors Based on Non-Uniformity Accesses.
Proceedings of the 2018 IEEE Canadian Conference on Electrical & Computer Engineering, 2018
2017
An energy efficient non-uniform Last Level Cache Architecture in 3D chip-multiprocessors.
Proceedings of the 18th International Symposium on Quality Electronic Design, 2017
A new traffic compression method for end-to-end memory accesses in 3D chip-multiprocessors.
Proceedings of the 30th IEEE Canadian Conference on Electrical and Computer Engineering, 2017
Exploiting non-uniformity of write accesses for designing a high-endurance hybrid Last Level Cache in 3D CMPs.
Proceedings of the 30th IEEE Canadian Conference on Electrical and Computer Engineering, 2017
2016
UCA: An Energy-efficient Hybrid Uncore Architecture in 3D Chip-Multiprocessors to minimize crosstalk.
Proceedings of the 9th International Workshop on Network on Chip Architectures, 2016