Pouya Taatizadeh

According to our database, Pouya Taatizadeh authored at least 6 papers between 2012 and 2017.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2017

Emulation Infrastructure for the Evaluation of Hardware Assertions for Post-Silicon Validation.

Pouya Taatizadeh, Nicola Nicolici

IEEE Trans. Very Large Scale Integr. Syst., 2017

An automated SAT-based method for the design of on-chip bit-flip detectors.

Pouya Taatizadeh, Nicola Nicolici

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

2016

Automated Selection of Assertions for Bit-Flip Detection During Post-Silicon Validation.

Pouya Taatizadeh, Nicola Nicolici

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

2015

Emulation-based selection and assessment of assertion checkers for post-silicon validation.

Pouya Taatizadeh, Nicola Nicolici

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

A methodology for automated design of embedded bit-flips detectors in post-silicon validation.

Pouya Taatizadeh, Nicola Nicolici

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2012

Automated critical device identification for configurable analogue transistors.

Robert Rudolf, Pouya Taatizadeh, Reuben Wilcock, Peter R. Wilson

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012