Praveena Murugesan

Orcid: 0000-0002-1334-9098

According to our database1, Praveena Murugesan authored at least 4 papers between 2013 and 2025.

Collaborative distances:
  • Dijkstra number2 of six.
  • Erdős number3 of six.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2025
Energy-Efficient and Area-Optimized Reversible Carry Select Adder.
IET Circuits Devices Syst., 2025

2016
Design of Efficient Reversible BCD Adder-Subtractor Architecture and Its Optimization Using Carry Skip Logic.
J. Circuits Syst. Comput., 2016

2014
Design of Optimal Carry Skip Adder and Carry Skip BCD Adder using Reversible Logic Gates.
J. Comput. Sci., 2014

2013
Enhanced Load Balancing Strategy in Heterogeneous Peer-to-Peer Networks.
J. Comput. Sci., 2013


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