Praveena Murugesan
Orcid: 0000-0002-1334-9098
According to our database1,
Praveena Murugesan authored at least 4 papers
between 2013 and 2025.
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Bibliography
2025
IET Circuits Devices Syst., 2025
2016
Design of Efficient Reversible BCD Adder-Subtractor Architecture and Its Optimization Using Carry Skip Logic.
J. Circuits Syst. Comput., 2016
2014
Design of Optimal Carry Skip Adder and Carry Skip BCD Adder using Reversible Logic Gates.
J. Comput. Sci., 2014
2013
J. Comput. Sci., 2013