Puguang Liu
Orcid: 0000-0002-7165-9297
According to our database1,
Puguang Liu authored at least 9 papers
between 2018 and 2026.
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Bibliography
2026
Blocking Is Not Stagnation: A Synchronous FPGA-CPU Architecture for Regular Expression Matching in Real-Time DPI.
IEEE Trans. Netw., 2026
2025
Enhancing Transformer Inference Efficiency on FPGA Through Fully Fusion and Integer-Only Quantization Techniques.
Proceedings of the 43rd IEEE International Conference on Computer Design, 2025
PSCA: A FPGA-based Protein Structure Comparison Accelerator with Symmetric Simplified Matrix.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2025
FPAMM: Fine-Grained Pipeline Architecture Accelerator for the Novel Transformer Architecture - Monarch Mixer.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2025
2024
Proceedings of the IEEE International Symposium on Circuits and Systems, 2024
2022
Reducing Network Traffic Storage Overhead: A Hardware-Accelerated Lossless Data Compression System.
Proceedings of the 6th Asia-Pacific Workshop on Networking, 2022
2021
MXQN: Mixed quantization for reducing bit-width of weights and activations in deep convolutional neural networks.
Appl. Intell., 2021
2019
Int. J. Distributed Sens. Networks, 2019
2018
Mitigating DoS Attacks Against Pseudonymous Authentication Through Puzzle-Based Co-Authentication in 5G-VANET.
IEEE Access, 2018