Qianxian Liao

According to our database, Qianxian Liao authored at least 5 papers between 2023 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2025

An Ultra-Low-Voltage Bias-Current-Free Fractional-N Hybrid PLL With Voltage-Mode Phase Detection and Interpolation.

Liqun Feng, Xuansheng Ji, Longhao Kuang, Qianxian Liao, Su Han, Jiahao Zhao, Woogeun Rhee, Zhihua Wang

IEEE J. Solid State Circuits, January, 2025

A 0.5V 0.55mm² Bias-Current-Free BLE Transceiver with 1-Bit Delay-Based Demodulation for Energy-Harvesting IoT applications.

Liqun Feng, Xuansheng Ji, Qianxian Liao, Longhao Kuang, Yunzhao Nie, Jiahao Zhao, Woogeun Rhee, Zhihua Wang

Proceedings of the IEEE Custom Integrated Circuits Conference, 2025

2024

14.7 A 0.45V 0.72mW 2.4GHz Bias-Current-Free Fractional-N Hybrid PLL Using a Voltage-Mode Phase Interpolator in 28nm CMOS.

Liqun Feng, Xuansheng Ji, Longhao Kuang, Qianxian Liao, Su Han, Jiahao Zhao, Woogeun Rhee, Zhihua Wang

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

A 0.6V Fully-Integrated BLE Transmitter in 65nm CMOS Using a Common-Mode-Ripple-Cancelled Hybrid PLL and a Duty-Cycle-Controlled Class-E/F2 PA Achieving 25% System Efficiency at 0dBm.

Liqun Feng, Qianxian Liao, Longhao Kuang, Jiahao Zhao, Woogeun Rhee, Zhihua Wang

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2024

2023

A Low-Voltage Bias-Current-Free Pseudo-Differential Hybrid PLL Using a Time-Interleaving Flip-Flop Phase Detector.

Liqun Feng, Qianxian Liao, Woogeun Rhee, Zhihua Wang

Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023