Woogeun Rhee

According to our database1, Woogeun Rhee authored at least 94 papers between 1999 and 2020.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2020
Frequency-Domain Modeling and Analysis of Injection-Locked Oscillators.
IEEE J. Solid State Circuits, 2020

A 6.5-8.1-GHz Communication/Ranging VWB Transceiver for Secure Wireless Connectivity With Enhanced Bandwidth Efficiency and ΔΣ Energy Detection.
IEEE J. Solid State Circuits, 2020

A 5.4GHz ΔΣ Bang-Bang PLL with 19dB In-Band Noise Reduction by Using a Nested PLL Filter.
Proceedings of the 2020 International Symposium on VLSI Design, Automation and Test, 2020

A Correlation-based Timing Skew Calibration Strategy Using a Time-Interleaved Reference ADC.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

A 13-bit 312.5-MS/s Pipelined SAR ADC with Integrator-type Residue Amplifier and Inter-stage Gain Stabilization Technique.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

A Low-Spur Current-Biasing-Free Fractional-N Hybrid PLL for Low-Voltage Clock Generation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

A 6-8GHz Multichannel Reconfigurable Pulse-Based Transceiver with 3.5ns Processing Latency and 1cm Ranging Accuracy for Secure Wireless Connectivity.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020

2019
A Capacitor-Less Ripple-Less Hybrid LDO With Exponential Ratio Array and 4000x Load Current Range.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

A 3.7-mW 2.4-GHz Phase-Tracking GFSK Receiver With BBPLL-Based Demodulation.
IEEE J. Solid State Circuits, 2019

Design and Analysis of Data-Pattern-Insensitive Phase-Tracking Receivers with Fully-Balanced FSK Modulation.
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019

A 9mW 6-9GHz 2.5Gb/s Proximity Transmitter with Combined OOK/BPSK Modulation for Low Power Mobile Connectivity.
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019

A Noise and Spur Reduction Technique for ΔΣ Fractional-N Bang-Bang PLLs with Embedded Phase Domain Filtering.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

A Gaussian-Filtered Fully-Balanced FSK Modulator with Integer-N PLL Based 1<sup>+</sup>-Point Modulation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

A 5GHz 200kHz/5000ppm Spread-Spectrum Clock Generator with Calibration-Free Two-Point Modulation Using a Nested-Loop BBPLL.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019

A 100Mb/s 3.5GHz Fully-Balanced BFOOK Modulator Based on Integer-N Hyrbrid PLL.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019

2018
400-MHz/2.4-GHz Combo WPAN Transceiver IC for Simultaneous Dual-Band Communication With One Single Antenna.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A 1-GHz 1.6-mW Auto-Calibrated Bit Slicer for Energy/Envelope Detection Receivers.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

A 120 pJ/bit ΔΣ-Based 2.4-GHz Transmitter Using FIR-Embedded Digital Power Amplifier.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

A 5-mW 750-kb/s Noninvasive Transceiver for Around-the-Head Audio Applications.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

A 77-GHz Mixed-Mode FMCW Signal Generator Based on Bang-Bang Phase Detector.
IEEE J. Solid State Circuits, 2018

A ΔΣ DPLL with 1b TDC, 4b DTC and 8-tap FIR filter for low-voltage clock generation/modulation systems.
Proceedings of the 2018 International Symposium on VLSI Design, 2018

A 26.6mW 1Gb/s dual-antenna wideband receiver with auto beam steering for secure proximity communications.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

A 6-8GHZ 200MHz Bandwidth 9-Channel VWB Transceiver with 8 Frequency-Hopping Subbands.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018

2017
A 17 mW 3-to-5 GHz Duty-Cycled Vital Sign Detection Radar Transceiver With Frequency Hopping and Time-Domain Oversampling.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017

A 1.9-mW 750-kb/s 2.4-GHz F-OOK Transmitter With Symmetric FM Template and High-Point Modulation PLL.
IEEE J. Solid State Circuits, 2017

A 0.42-mW 1-Mb/s 3- to 4-GHz Transceiver in 0.18-µm CMOS With Flexible Efficiency, Bandwidth, and Distance Control for IoT Applications.
IEEE J. Solid State Circuits, 2017

An energy/bandwidth/area efficient frequency-domain OOK transmitter with phase rotated modulation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A 0.6V 50-to-145MHz PVT tolerant digital PLL with DCO-dedicated ΔΣ LDO and temperature compensation circuits in 65nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

A 6.1mW 5Mb/s 2.4GHz transceiver with F-OOK modulation for high bandwidth and energy efficiencies.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

Session 15 - Energy-efficient wireless for 5G and IoT.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

A 77-GHz mixed-mode FMCW signal generator based on bang-bang phase detector.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017

2016
An overview of digital-intensive ΔΣ phase-locked loops utilizing 1-bit conversion and modulation.
Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016

EE4: Eureka! The best moments of solid-state circuit design in the 2000s.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

A 1.9mW 750kb/s 2.4GHz F-OOK transmitter with symmetric FM template and high-point modulation PLL.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015
A 0.35-0.5-V 18-152 MHz Digitally Controlled Relaxation Oscillator With Adaptive Threshold Calibration in 65-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2015

A 13.3 mW 500 Mb/s IR-UWB Transceiver With Link Margin Enhancement Technique for Meter-Range Communications.
IEEE J. Solid State Circuits, 2015

A high-PSRR ADPLL with self-regulated GRO TDC and DCO-dedicated voltage regulator.
Proceedings of the VLSI Design, Automation and Test, 2015

A delta-sigma-based transmitter utilizing FIR-embedded digital power amplifiers.
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

A digital power amplifier with FIR-embedded 1-Bit high-order ΔΣ modulation for WBAN polar transmitters.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A multi-bit FIR filtering technique for two-point modulators with dedicated digital high-pass modulation path.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Phase-locked frequency synthesis and modulation for modern wireless transceivers.
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015

A spread-spectrum clock generator with FIR-embedded binary phase detection and 1-bit high-order ΔΣ modulation.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

A 7.6mW 2Gb/s proximity transmitter for smartphone-mirrored display applications.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015

A 2.4 GHz two-point Δ-Σ modulator with gain calibration and AFC for WPAN/BAN applications.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015

2014
A 4.8-mW/Gb/s 9.6-Gb/s 5 + 1-Lane Source-Synchronous Transmitter in 65-nm Bulk CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

A PSRR Enhancing Method for GRO TDC Based Clock Generation Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014

A ΔΣ-TDC-Based Beamforming Method for Vital Sign Detection Radar Systems.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

A Hybrid Loop Two-Point Modulator Without DCO Nonlinearity Calibration by Utilizing 1 Bit High-Pass Modulation.
IEEE J. Solid State Circuits, 2014

A 1.5GHz all-digital frequency-locked loop with 1-bit ΔΣ frequency detection in 0.18μm CMOS.
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

A 3.5-4GHz FMCW radar transceiver design with phase-domain oversampled ranging by utilizing a 1-bit ΔΣ TDC.
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014

F5: Low-power radios for sensor networks.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

9.2 A 13.3mW 500Mb/s IR-UWB transceiver with link-margin enhancement technique for meter-range communications.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

9.3 A 1mW 1Mb/s 7.75-to-8.25GHz chirp-UWB transceiver with low peak-power transmission and fast synchronization capability.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

A high efficiency robust IR-UWB receiver design for high data rate CM-range communications.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

A 2.5GHz ADPLL with PVT-insensitive ΔΣ dithered time-to-digital conversion by utilizing an ADDLL.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Algorithm-Based Countermeasures against Power Analysis Attacks for Public-Key Cryptography SM2.
Proceedings of the Tenth International Conference on Computational Intelligence and Security, 2014

A 0.65V 1.2mW 2.4GHz/400MHz dual-mode phase modulator for mobile healthcare applications.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014

2013
Reconfigurable FM-UWB transmitter design for robust short range communications.
Telecommun. Syst., 2013

A Phase-Domain ΔΣ Ranging Method for FMCW Radar Receivers.
IEEE Trans. Circuits Syst. II Express Briefs, 2013

A 5.2-11.8MHz octa-phase relaxation oscillator for 8-PSK FM-UWB transceiver systems.
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013

An FM-UWB transceiver with M-PSK subcarrier modulation and regenerative FM demodulation.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013

A PLL/DLL based CDR with ΔΣ frequency tracking and low algorithmic jitter generation.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A 1.14mW 750kb/s FM-UWB transmitter with 8-FSK subcarrier modulation.
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2012
A Gated FM-UWB System With Data-Driven Front-End Power Control.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

A Dual-Channel Compass/GPS/GLONASS/Galileo Reconfigurable GNSS Receiver in 65 nm CMOS With On-Chip I/Q Calibration.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012

Introduction to the Special Section on the 2011 Asian Solid-State Circuits Conference (A-SSCC).
IEEE J. Solid State Circuits, 2012

Clock/Frequency Generation Circuits and Systems.
J. Electr. Comput. Eng., 2012

A PVT-insensitive self-dithered TDC design by utilizing a ΔΣ DLL.
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012

Session 26 overview: Short-range wireless transceivers: Wireless subcommittee.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A ΔΣ IR-UWB radar with sub-mm ranging capability for human body monitoring systems.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A 9.6Gb/s 5+1-lane source synchronous transmitter in 65nm CMOS technology.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

A pulse-shaped power amplifier with dynamic bias switching for IR-UWB transmitters.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
A Continuously Tunable Hybrid LC-VCO PLL With Mixed-Mode Dual-Path Control and Bi-level Delta-Sigma Modulated Coarse Tuning.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011

Semidigital PLL Design for Low-Cost Low-Power Clock Generation.
J. Electr. Comput. Eng., 2011

A wide-tuning quasi-type-I PLL with voltage-mode frequency acquisition aid.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A relaxation oscillator with multi-phase triangular waveform generation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010
Low power, non invasive UWB systems for WBAN and biomedical applications.
Proceedings of the International Conference on Information and Communication Technology Convergence, 2010

Power and jitter optimized VCO design using an on-chip supply noise monitoring circuit.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

Reconfigurable, fast AFC technique using code estimation and binary search algorithm for 0.2-6GHz software-defined radio frequency synthesis.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2009
An FIR-Embedded Noise Filtering Method for ΔΣ Fractional-N PLL Clock Generators.
IEEE J. Solid State Circuits, 2009

A ΔΣ Fractional-N Synthesizer With Customized Noise Shaping for WCDMA/HSDPA Applications.
IEEE J. Solid State Circuits, 2009

A Hybrid Spur Compensation Technique for Finite-Modulo Fractional-N Phase-Locked Loops.
IEEE J. Solid State Circuits, 2009

A 0.4-to-1.6GHz low-OSR ΔΣ DLL with self-referenced multiphase generation.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

Customized Zero Frequency Control for Hybrid FIR Noise Filtering in SigmaDelta Fractional-N PLL.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Transient Analysis of Nonlinear Settling Behavior in Charge-pump Phase-locked Loop Design.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008
Experimental Analysis of Substrate Noise Effect on PLL Performance.
IEEE Trans. Circuits Syst. II Express Briefs, 2008

A 1GHz Fractional-N PLL Clock Generator with Low-OSR ΔΣ Modulation and FIR-Embedded Noise Filtering.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007
An Ultra-Compact Differentially Tuned 6-GHz CMOS LC-VCO With Dynamic Common-Mode Feedback.
IEEE J. Solid State Circuits, 2007

All-Digital Dynamic Self-Detection and Self-Compensation of Static Phase Offsets in Charge-Pump PLLs.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A Fractional-N PLL for Digital Clock Generation With an FIR-Embedded Frequency Divider.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006
A 10Gb/s 5-Tap-DFE/4-Tap-FFE Transceiver in 90nm CMOS.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2004
A semi-digital delay-locked loop using an analog-based finite state machine.
IEEE Trans. Circuits Syst. II Express Briefs, 2004

1999
An on-chip phase compensation technique in fractional-N frequency synthesis.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Design of low-jitter 1-GHz phase-locked loops for digital clock generation.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999


  Loading...