Woogeun Rhee
Orcid: 0000-0003-2473-4132
According to our database1,
Woogeun Rhee
authored at least 123 papers
between 1999 and 2024.
Collaborative distances:
Collaborative distances:
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Bibliography
2024
A 0.14-nJ/b 200-Mb/s 2.7-3.5-GHz Quasi-Balanced FSK Transceiver With PLL-Based Modulation and Sideband Energy Detection.
IEEE Trans. Circuits Syst. I Regul. Pap., April, 2024
A DTC-Free Fractional-N BBPLL With FIR-Embedded Injection-Locked-Oscillator-Based Phase-Domain Lowpass Filter.
IEEE J. Solid State Circuits, March, 2024
14.7 A 0.45V 0.72mW 2.4GHz Bias-Current-Free Fractional-N Hybrid PLL Using a Voltage-Mode Phase Interpolator in 28nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024
2023
A 0.061-pJ/b/dB 28-Gb/s Gradient-Based Maximum Eye Tracking CDR With 2-Tap DFE Adaptation in 28-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, November, 2023
Proceedings of the IEEE International Solid- State Circuits Conference, 2023
A 405ps/20% Delay Range, 7.4mW/ns BPF-Based Delay Cell with ISI Mitigation for 7.5-8.5GHz IR-UWB Beamforming Receivers.
Proceedings of the IEEE International Conference on Integrated Circuits, 2023
A 17.3mW IEEE 802.15.4/4z Coherent Quadrature Hybrid Correlation UWB Receiver in 65nm CMOS.
Proceedings of the 49th IEEE European Solid State Circuits Conference, 2023
A 2.6GHz ΔΣ Fractional-N Bang-Bang PLL with FIR-Embedded Injection-Locking Phase-Domain Low-Pass Filter.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023
A Low-Voltage Bias-Current-Free Pseudo-Differential Hybrid PLL Using a Time-Interleaving Flip-Flop Phase Detector.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2023
2022
A Quantization Noise Reduction Method for Delta-Sigma Fractional-N PLLs Using Cascaded Injection-Locked Oscillators.
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A 13-Bit 2-GS/s Time-Interleaved ADC With Improved Correlation-Based Timing Skew Calibration Strategy.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
Guest Editorial Introduction to the Special Section on the 2021 Asian Solid-State Circuits Conference (A-SSCC).
IEEE J. Solid State Circuits, 2022
An 8GHz Communication/Ranging IR-UWB Transmitter with Asymmetric Pulse Shaping and Frequency Hopping for Fine Ranging and Enhanced Link Margin.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
A 0.7-2.5GHz NB-loT/GNSS/BLE Hybrid PLL with PA Pulling Mitigation and Out-of-Band Phase Noise Reduction.
Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022
An Analog-Assisted Digital LDO with 0.37mV Output Ripple and 5500x Load Current Range in 180nm CMOS.
Proceedings of the 2022 IEEE International Conference on Integrated Circuits, 2022
A 7.25-7.75GHz 5.9mW UWB Transceiver with -23.8dBm NBI Tolerance and 1.5cm Ranging Accuracy Using Uncertain IF and Pulse-Triggered Envelope/Energy Detection.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
A 0.14nJ/b 200Mb/s Quasi-Balanced FSK Transceiver with Closed-Loop Modulation and Sideband Energy Detection.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2022
2021
A 2.4-GHz Crystal-Less GFSK Receiver Using an Auxiliary Multiphase BBPLL for Digital Output Demodulation With Enhanced Frequency Scaling.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
A 0.0048mm<sup>2</sup> 0.43-to-1.0V 0.54-to-1.76GHz Bias-Current-Free PLL in 14nm FinFET CMOS.
Proceedings of the 2021 IEEE International Conference on Integrated Circuits, 2021
2020
IEEE J. Solid State Circuits, 2020
A 6.5-8.1-GHz Communication/Ranging VWB Transceiver for Secure Wireless Connectivity With Enhanced Bandwidth Efficiency and ΔΣ Energy Detection.
IEEE J. Solid State Circuits, 2020
A 5.4GHz ΔΣ Bang-Bang PLL with 19dB In-Band Noise Reduction by Using a Nested PLL Filter.
Proceedings of the 2020 International Symposium on VLSI Design, Automation and Test, 2020
A Correlation-based Timing Skew Calibration Strategy Using a Time-Interleaved Reference ADC.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020
A 13-bit 312.5-MS/s Pipelined SAR ADC with Integrator-type Residue Amplifier and Inter-stage Gain Stabilization Technique.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020
A Low-Spur Current-Biasing-Free Fractional-N Hybrid PLL for Low-Voltage Clock Generation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
A Nonlinearity-Calibration-Free Reconfigurable ADPLL for General Purpose Frequency Modulation.
Proceedings of the 2020 IEEE International Conference on Integrated Circuits, 2020
A 6-8GHz Multichannel Reconfigurable Pulse-Based Transceiver with 3.5ns Processing Latency and 1cm Ranging Accuracy for Secure Wireless Connectivity.
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020
2019
A Capacitor-Less Ripple-Less Hybrid LDO With Exponential Ratio Array and 4000x Load Current Range.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
IEEE J. Solid State Circuits, 2019
Design and Analysis of Data-Pattern-Insensitive Phase-Tracking Receivers with Fully-Balanced FSK Modulation.
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019
A 9mW 6-9GHz 2.5Gb/s Proximity Transmitter with Combined OOK/BPSK Modulation for Low Power Mobile Connectivity.
Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019
A Noise and Spur Reduction Technique for ΔΣ Fractional-N Bang-Bang PLLs with Embedded Phase Domain Filtering.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
A Gaussian-Filtered Fully-Balanced FSK Modulator with Integer-N PLL Based 1<sup>+</sup>-Point Modulation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
A 5GHz 200kHz/5000ppm Spread-Spectrum Clock Generator with Calibration-Free Two-Point Modulation Using a Nested-Loop BBPLL.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2019
2018
400-MHz/2.4-GHz Combo WPAN Transceiver IC for Simultaneous Dual-Band Communication With One Single Antenna.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
IEEE Trans. Circuits Syst. II Express Briefs, 2018
A 120 pJ/bit ΔΣ-Based 2.4-GHz Transmitter Using FIR-Embedded Digital Power Amplifier.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
IEEE Trans. Circuits Syst. II Express Briefs, 2018
IEEE J. Solid State Circuits, 2018
A ΔΣ DPLL with 1b TDC, 4b DTC and 8-tap FIR filter for low-voltage clock generation/modulation systems.
Proceedings of the 2018 International Symposium on VLSI Design, 2018
A 26.6mW 1Gb/s dual-antenna wideband receiver with auto beam steering for secure proximity communications.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018
A 6-8GHZ 200MHz Bandwidth 9-Channel VWB Transceiver with 8 Frequency-Hopping Subbands.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
2017
A 17 mW 3-to-5 GHz Duty-Cycled Vital Sign Detection Radar Transceiver With Frequency Hopping and Time-Domain Oversampling.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
A 1.9-mW 750-kb/s 2.4-GHz F-OOK Transmitter With Symmetric FM Template and High-Point Modulation PLL.
IEEE J. Solid State Circuits, 2017
A 0.42-mW 1-Mb/s 3- to 4-GHz Transceiver in 0.18-µm CMOS With Flexible Efficiency, Bandwidth, and Distance Control for IoT Applications.
IEEE J. Solid State Circuits, 2017
An energy/bandwidth/area efficient frequency-domain OOK transmitter with phase rotated modulation.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
A 0.6V 50-to-145MHz PVT tolerant digital PLL with DCO-dedicated ΔΣ LDO and temperature compensation circuits in 65nm CMOS.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
A 6.1mW 5Mb/s 2.4GHz transceiver with F-OOK modulation for high bandwidth and energy efficiencies.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
2016
An overview of digital-intensive ΔΣ phase-locked loops utilizing 1-bit conversion and modulation.
Proceedings of the IEEE 59th International Midwest Symposium on Circuits and Systems, 2016
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
A 1.9mW 750kb/s 2.4GHz F-OOK transmitter with symmetric FM template and high-point modulation PLL.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
2015
A 0.35-0.5-V 18-152 MHz Digitally Controlled Relaxation Oscillator With Adaptive Threshold Calibration in 65-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, 2015
A 13.3 mW 500 Mb/s IR-UWB Transceiver With Link Margin Enhancement Technique for Meter-Range Communications.
IEEE J. Solid State Circuits, 2015
Proceedings of the VLSI Design, Automation and Test, 2015
Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015
A digital power amplifier with FIR-embedded 1-Bit high-order ΔΣ modulation for WBAN polar transmitters.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
A multi-bit FIR filtering technique for two-point modulators with dedicated digital high-pass modulation path.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 2015 IEEE Custom Integrated Circuits Conference, 2015
A spread-spectrum clock generator with FIR-embedded binary phase detection and 1-bit high-order ΔΣ modulation.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2015
A 2.4 GHz two-point Δ-Σ modulator with gain calibration and AFC for WPAN/BAN applications.
Proceedings of the 2015 IEEE 11th International Conference on ASIC, 2015
2014
IEEE Trans. Circuits Syst. II Express Briefs, 2014
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
IEEE Trans. Circuits Syst. II Express Briefs, 2014
A Hybrid Loop Two-Point Modulator Without DCO Nonlinearity Calibration by Utilizing 1 Bit High-Pass Modulation.
IEEE J. Solid State Circuits, 2014
A 1.5GHz all-digital frequency-locked loop with 1-bit ΔΣ frequency detection in 0.18μm CMOS.
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014
A 3.5-4GHz FMCW radar transceiver design with phase-domain oversampled ranging by utilizing a 1-bit ΔΣ TDC.
Proceedings of the Technical Papers of 2014 International Symposium on VLSI Design, 2014
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
9.2 A 13.3mW 500Mb/s IR-UWB transceiver with link-margin enhancement technique for meter-range communications.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
9.3 A 1mW 1Mb/s 7.75-to-8.25GHz chirp-UWB transceiver with low peak-power transmission and fast synchronization capability.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
A high efficiency robust IR-UWB receiver design for high data rate CM-range communications.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
A 2.5GHz ADPLL with PVT-insensitive ΔΣ dithered time-to-digital conversion by utilizing an ADDLL.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Algorithm-Based Countermeasures against Power Analysis Attacks for Public-Key Cryptography SM2.
Proceedings of the Tenth International Conference on Computational Intelligence and Security, 2014
A 0.65V 1.2mW 2.4GHz/400MHz dual-mode phase modulator for mobile healthcare applications.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2014
2013
Telecommun. Syst., 2013
IEEE Trans. Circuits Syst. II Express Briefs, 2013
Proceedings of the 2013 International Symposium on VLSI Design, Automation, and Test, 2013
An FM-UWB transceiver with M-PSK subcarrier modulation and regenerative FM demodulation.
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013
A PLL/DLL based CDR with ΔΣ frequency tracking and low algorithmic jitter generation.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013
Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013
2012
IEEE Trans. Circuits Syst. I Regul. Pap., 2012
A Dual-Channel Compass/GPS/GLONASS/Galileo Reconfigurable GNSS Receiver in 65 nm CMOS With On-Chip I/Q Calibration.
IEEE Trans. Circuits Syst. I Regul. Pap., 2012
Introduction to the Special Section on the 2011 Asian Solid-State Circuits Conference (A-SSCC).
IEEE J. Solid State Circuits, 2012
Proceedings of the 55th IEEE International Midwest Symposium on Circuits and Systems, 2012
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2011
A Continuously Tunable Hybrid LC-VCO PLL With Mixed-Mode Dual-Path Control and Bi-level Delta-Sigma Modulated Coarse Tuning.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011
J. Electr. Comput. Eng., 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
2010
Proceedings of the International Conference on Information and Communication Technology Convergence, 2010
Power and jitter optimized VCO design using an on-chip supply noise monitoring circuit.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010
Reconfigurable, fast AFC technique using code estimation and binary search algorithm for 0.2-6GHz software-defined radio frequency synthesis.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010
2009
IEEE J. Solid State Circuits, 2009
A ΔΣ Fractional-N Synthesizer With Customized Noise Shaping for WCDMA/HSDPA Applications.
IEEE J. Solid State Circuits, 2009
A Hybrid Spur Compensation Technique for Finite-Modulo Fractional-N Phase-Locked Loops.
IEEE J. Solid State Circuits, 2009
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
Customized Zero Frequency Control for Hybrid FIR Noise Filtering in SigmaDelta Fractional-N PLL.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Transient Analysis of Nonlinear Settling Behavior in Charge-pump Phase-locked Loop Design.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
2008
IEEE Trans. Circuits Syst. II Express Briefs, 2008
A 1GHz Fractional-N PLL Clock Generator with Low-OSR ΔΣ Modulation and FIR-Embedded Noise Filtering.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
2007
An Ultra-Compact Differentially Tuned 6-GHz CMOS LC-VCO With Dynamic Common-Mode Feedback.
IEEE J. Solid State Circuits, 2007
All-Digital Dynamic Self-Detection and Self-Compensation of Static Phase Offsets in Charge-Pump PLLs.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
A Fractional-N PLL for Digital Clock Generation With an FIR-Embedded Frequency Divider.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
2006
IEEE J. Solid State Circuits, 2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
2005
IEEE J. Solid State Circuits, 2005
2004
IEEE Trans. Circuits Syst. II Express Briefs, 2004
2003
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003
2002
An 18-mW 2.5-GHz/900-MHz BiCMOS dual frequency synthesizer with <10-Hz RF carrier resolution.
IEEE J. Solid State Circuits, 2002
A single-chip quad-band (850/900/1800/1900 MHz) direct conversion GSM/GPRS RF transceiver with integrated VCOs and fractional-n synthesizer.
IEEE J. Solid State Circuits, 2002
2001
PhD thesis, 2001
2000
A 1.1-GHz CMOS fractional-N frequency synthesizer with a 3-b third-order ΔΣ modulator.
IEEE J. Solid State Circuits, 2000
1999
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999