Qing Dong

Affiliations:

University of Kitakyushu, Department of Information and Media Engineering, Wakamatsu, Japan

According to our database¹, Qing Dong authored at least 17 papers between 2008 and 2016.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of five.

Timeline

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Article

PhD thesis

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Links

On csauthors.net:

Bibliography

2016

DC Characteristics and Variability on 90nm CMOS Transistor Array-Style Analog Layout.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2016

2015

Layout Dependent Effect-Aware Leakage Current Reduction and Its Application to Low-Power SAR-ADC.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2015

Low-Power and Low-Variability Programmable Delay Element and Its Application to Post-Silicon Skew Tuning.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

2013

Analog Circuit Synthesis with Constraint Generation of Layout-Dependent Effects by Geometric Programming.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

Structured Analog Circuit and Layout Design with Transistor Array.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

Performance-driven SRAM macro design with parameterized cell considering layout-dependent effects.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013

A comparator energy model considering shallow trench isolation stress by geometric programming.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Quality Electronic Design, 2013

A 9-bit 50msps SAR ADC with pre-charge VCM -based double input range algorithm.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

2012

Transistor channel decomposition for structured analog layout, manufacturability and low-power applications.

[BibT_eX]

[DOI]

Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

2011

Layout-aware mismatch modeling for CMOS current sources with D/A converter analysis.

[BibT_eX]

[DOI]

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Layout-aware variation evaluation of analog circuits and its validity on op-amp designs.

[BibT_eX]

[DOI]

Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

2010

Post-placement STI well width adjusting by geometric programming for device mobility enhancement in critical path.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Structured analog circuit design and MOS transistor decomposition for high accuracy applications.

[BibT_eX]

[DOI]

Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

2009

Structured Placement with Topological Regularity Evaluation.

[BibT_eX]

[DOI]

Qing Dong

Shigetoshi Nakatake

IPSJ Trans. Syst. LSI Des. Methodol., 2009

Incremental Buffer Insertion and Module Resizing Algorithm Using Geometric Programming.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

STI stress aware placement optimization based on geometric programming.

[BibT_eX]

[DOI]

Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

2008

Constraint-free analog placement with topological symmetry structure.

[BibT_eX]

[DOI]

Qing Dong

Shigetoshi Nakatake

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

Qing Dong

Timeline

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On csauthors.net:

Bibliography

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