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R. K. Kavitha

Orcid: 0000-0002-2480-0876

According to our database1, R. K. Kavitha authored at least 5 papers between 2013 and 2020.

Collaborative distances:
  • Dijkstra number2 of six.
  • Erdős number3 of six.

Timeline

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Links

On csauthors.net:

Bibliography

2020
High-performance asynchronous pipeline using embedded delay element.
[BibTeX]
[DOI]
R. K. Kavitha
,
A. Khajamastan
,
Y. Rama Akhilesh
,
B. Venkataramani
Microprocess. Microsystems, 2020

2017
Low Power Data Driven Conditional Precharge Dynamic Flip Flop.
[BibTeX]
[DOI]
R. K. Kavitha
,
Vineeth Johns Toms
,
Vipin Vinayakan
,
B. Venkataramani
J. Low Power Electron., 2017

2015
Knowledge sharing through pair programming in learning environments: An empirical study.
[BibTeX]
[DOI]
R. K. Kavitha
,
M. S. Irfan Ahmed
Educ. Inf. Technol., 2015

2014
High-Speed Dynamic Asynchronous Pipeline: Self-Precharging Style.
[BibTeX]
[DOI]
C. K. Midhun
,
Jephy Joy
,
R. K. Kavitha
IEEE Trans. Very Large Scale Integr. Syst., 2014

2013
Low-Power Dual Dynamic Node Pulsed Hybrid Flip-Flop Featuring Efficient Embedded Logic.
[BibTeX]
[DOI]
Kalarikkal Absel
,
Lijo Manuel
,
R. K. Kavitha
IEEE Trans. Very Large Scale Integr. Syst., 2013


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