R. Marimuthu

According to our database, R. Marimuthu authored at least 7 papers between 2012 and 2018.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2018

Design of 5-3 multicolumn compressor for high performance multiplier.

R. Marimuthu, S. Balamurugan, Partha Sharathi Mallick

Int. J. Comput. Aided Eng. Technol., 2018

Design of High Speed 5: 2 and 7: 2 Compressor Using Nanomagnetic Logic.

Shantanu Agarwal, G. Harish, S. Balamurugan, R. Marimuthu

Proceedings of the VLSI Design and Test - 22nd International Symposium, 2018

Realization of 2-D DCT Using Adder Compressor.

Raunak R. Lahoti, Shantanu Agarwal, S. Balamurugan, R. Marimuthu

Proceedings of the Soft Computing for Problem Solving, 2018

Design and Analysis of 4-Bit Squarer Circuit Using Minority and Majority Logic in MagCAD.

Saurabh Kumar, R. Marimuthu, S. Balamurugan

Proceedings of the Soft Computing for Problem Solving, 2018

2017

Design and Analysis of Multiplier Using Approximate 15-4 Compressor.

R. Marimuthu, Y. Elsie Rezinold, Partha Sharathi Mallick

IEEE Access, 2017

2012

Design of low power fixed-width multiplier with row bypassing.

S. Balamurugan, Sneha Ghosh, Atul, Balakumaran Srirangaswamy, R. Marimuthu, Partha Sharathi Mallick

IEICE Electron. Express, 2012

FPGA design and implementation of truncated multipliers using bypassing technique.

S. Balamurugan, Balakumaran Srirangaswamy, R. Marimuthu, Partha Sharathi Mallick

Proceedings of the 2012 International Conference on Advances in Computing, 2012