R. V. K. Pillai

According to our database, R. V. K. Pillai authored at least 8 papers between 1996 and 2001.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2001

A Low Power Approach to Floating Point Adder Design for DSP Applications.

R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili, S. Y. A. Shah

J. VLSI Signal Process., 2001

Low power floating point MAFs-a comparative study.

R. V. K. Pillai, S. Y. A. Shah, A. J. Al-Khalili, Dhamin Al-Khalili

Proceedings of the Sixth International Symposium on Signal Processing and its Applications, 2001

1999

Power implications of precision limited arithmetic in floating point FIR filters.

R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

An IEEE Compliant Floating Point MAF.

R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili

Proceedings of the VLSI: Systems on a Chip, 1999

1998

A Low Power Floating Point Accumulator.

R. V. K. Pillai, Asim J. Al-Khalili, Dhamin Al-Khalili

Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

1997

Energy delay measures of barrel switch architectures for pre-alignment of floating point operands for addition.

R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili

Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997

A Low Power Approach to Floating Point Adder Design.

R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili

Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997

1996

Energy delay analysis of partial product reduction methods for parallel multiplier implementation.

R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili

Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996