# Radu Iosif

According to our database

Collaborative distances:

^{1}, Radu Iosif authored at least 41 papers between 1999 and 2018.Collaborative distances:

## Timeline

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## Bibliography

2018

Abstraction Refinement for Emptiness Checking of Alternating Data Automata.

Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2018

Program Verification with Separation Logic.

Proceedings of the Model Checking Software - 25th International Symposium, 2018

2017

Reasoning in the Bernays-Schönfinkel-Ramsey Fragment of Separation Logic.

Proceedings of the Verification, Model Checking, and Abstract Interpretation, 2017

2016

Abstraction Refinement and Antichains for Trace Inclusion of Infinite State Systems.

Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2016

A Decision Procedure for Separation Logic in SMT.

Proceedings of the Automated Technology for Verification and Analysis, 2016

How Hard is It to Verify Flat Affine Counter Systems with the Finite Monoid Property?

Proceedings of the Automated Technology for Verification and Analysis, 2016

2015

Interprocedural Reachability for Flat Integer Programs.

Proceedings of the Fundamentals of Computation Theory - 20th International Symposium, 2015

2014

Deciding Conditional Termination

Logical Methods in Computer Science, 2014

Safety Problems Are NP-complete for Flat Integer Programs with Octagonal Loops.

Proceedings of the Verification, Model Checking, and Abstract Interpretation, 2014

Deciding Entailments in Inductive Separation Logic with Tree Automata.

Proceedings of the Automated Technology for Verification and Analysis, 2014

2013

Underapproximation of Procedure Summaries for Integer Programs.

Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2013

The Tree Width of Separation Logic with Recursive Definitions.

Proceedings of the Automated Deduction - CADE-24, 2013

2012

Deciding Conditional Termination.

Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2012

A Verification Toolkit for Numerical Transition Systems - Tool Paper.

Proceedings of the FM 2012: Formal Methods, 2012

Accelerating Interpolants.

Proceedings of the Automated Technology for Verification and Analysis, 2012

2010

Fast Acceleration of Ultimately Periodic Relations.

Proceedings of the Computer Aided Verification, 22nd International Conference, 2010

Tool Demonstration of the FLATA Counter Automata Toolset.

Proceedings of the Second International Workshop on Invariant Generation, 2010

2009

Automata-Based Termination Proofs.

Proceedings of the Implementation and Application of Automata, 2009

Iterating Octagons.

Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2009

Automatic Verification of Integer Array Programs.

Proceedings of the Computer Aided Verification, 21st International Conference, 2009

2008

A Logic of Singly Indexed Arrays.

Proceedings of the Logic for Programming, 2008

What Else Is Decidable about Integer Arrays?.

Proceedings of the Foundations of Software Science and Computational Structures, 2008

Quantitative Separation Logic and Programs with Lists.

Proceedings of the Automated Reasoning, 4th International Joint Conference, 2008

2007

On Flat Programs with Lists.

Proceedings of the Verification, 2007

Proving Termination of Tree Manipulating Programs.

Proceedings of the Automated Technology for Verification and Analysis, 2007

2006

Automata-Based Verification of Programs with Tree Updates.

Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2006

Flat Parametric Counter Automata.

Proceedings of the Automata, Languages and Programming, 33rd International Colloquium, 2006

Programs with Lists Are Counter Automata.

Proceedings of the Computer Aided Verification, 18th International Conference, 2006

2005

Translating Java for Multiple Model Checkers: The Bandera Back-End.

Formal Methods in System Design, 2005

On Decidability Within the Arithmetic of Addition and Divisibility.

Proceedings of the Foundations of Software Science and Computational Structures, 2005

2004

Symmetry reductions for model checking of concurrent dynamic software.

STTT, 2004

On Logics of Aliasing.

Proceedings of the Static Analysis, 11th International Symposium, 2004

2003

Space-Reduction Strategies for Model Checking Dynamic Software.

Electr. Notes Theor. Comput. Sci., 2003

Storeless semantics and alias logic.

Proceedings of the 2003 ACM SIGPLAN Workshop on Partial Evaluation and Semantics-based Program Manipulation, 2003

2002

Symmetry Reduction Criteria for Software Model Checking.

Proceedings of the Model Checking of Software, 2002

2001

Temporal Logic Properties of Java Objects.

Proceedings of the Thirteenth International Conference on Software Engineering & Knowledge Engineering (SEKE'2001), 2001

Exploiting Heap Symmetries in Explicit-State Model Checking of Software.

Proceedings of the 16th IEEE International Conference on Automated Software Engineering (ASE 2001), 2001

2000

Using Garbage Collection in Model Checking.

Proceedings of the SPIN Model Checking and Software Verification, 7th International SPIN Workshop, Stanford, CA, USA, August 30, 2000

Formal verification applied to Java concurrent software.

Proceedings of the 22nd International Conference on on Software Engineering, 2000

1999

A Deadlock Detection Tool for Concurrent Java Programs.

Softw., Pract. Exper., 1999

dSPIN: A Dynamic Extension of SPIN.

Proceedings of the Theoretical and Practical Aspects of SPIN Model Checking, 1999