Rahul Bhattacharya

Orcid: 0000-0001-9937-0308

According to our database1, Rahul Bhattacharya authored at least 7 papers between 2010 and 2023.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

2023
MATLAB-Open Source Tool Based Framework for Test Generation for Digital Circuits Using Evolutionary Algorithms.
J. Electron. Test., December, 2023

2022
Introducing flexible perovskites to the IoT world using photovoltaic-powered wireless tags.
CoRR, 2022

2017
Resource optimization for emulation of behavioral models of mixed signal circuits on FPGA: a case study of DC-DC buck converter.
Int. J. Circuit Theory Appl., 2017

SFG Based Fault Simulation of Linear Analog Circuits Using Fault Classification and Sensitivity Analysis.
Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

2016
Characterizing Non-nesting for the Neyman-Pearson Family of Tests.
J. Stat. Theory Appl., 2016

2015
A randomized two stage allocation for continuous response clinical trials.
Stat. Methods Appl., 2015

2010
FPGA based chip emulation system for test development and verification of analog and mixed signal circuits (abstract only).
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010


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