Santosh Biswas

Orcid: 0000-0003-3020-4154

According to our database1, Santosh Biswas authored at least 139 papers between 2004 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
A hybrid IDS for detection and mitigation of sinkhole attack in 6LoWPAN networks.
Int. J. Inf. Sec., April, 2024

2023
Incomplete Testing of SOC.
J. Electron. Test., June, 2023

OPTIMIST: Lightweight and Transparent IDS With Optimum Placement Strategy to Mitigate Mixed-Rate DDoS Attacks in IoT Networks.
IEEE Internet Things J., May, 2023

On Securing Cryptographic ICs against Scan-based Attacks: A Hamming Weight Distribution Perspective.
ACM J. Emerg. Technol. Comput. Syst., April, 2023

DADCNF: Diagnoser design for Duplicate Address Detection threat using Conjunctive Normal Form.
Comput. Networks, February, 2023

A protocol to establish trust on biometric authentication devices.
Secur. Priv., 2023

Effective injection of adversarial botnet attacks in IoT ecosystem using evolutionary computing.
Internet Technol. Lett., 2023

LDES: detector design for version number attack detection using linear temporal logic based on discrete event system.
Int. J. Inf. Sec., 2023

A Novel Energy-Efficient Scheme for RPL Attacker Identification in IoT Networks Using Discrete Event Modeling.
IEEE Access, 2023

2022
Fault Localization Scheme for Missing Gate Faults in Reversible Circuits.
ACM Trans. Design Autom. Electr. Syst., 2022

Accelerating NoC Verification Using a Complete Model and Active Window.
IEEE Access, 2022

Non-preemptive Real-time Task Scheduling on Heterogeneous Systems - A Supervisory Control Based Optimal Approach.
Proceedings of the European Control Conference, 2022

2021
Effect of awareness program on diabetes mellitus: deterministic and stochastic approach.
J. Appl. Math. Comput., June, 2021

Fault-Tolerant Real-Time Fair Scheduling on Multiprocessor Systems with Cold-Standby.
IEEE Trans. Dependable Secur. Comput., 2021

Optimal work-conserving scheduler synthesis for real-time sporadic tasks using supervisory control of timed discrete-event systems.
J. Sched., 2021

Fragmented software-based self-test technique for online intermittent fault detection in processors.
IET Comput. Digit. Tech., 2021

Retesting Defective Circuits to Allow Acceptable Faults for Yield Enhancement.
J. Electron. Test., 2021

Automated Low-Cost SBST Optimization Techniques for Processor Testing.
Proceedings of the 34th International Conference on VLSI Design and 20th International Conference on Embedded Systems, 2021

ATPG for Incomplete Testing of SOC Considering Bridging Faults.
Proceedings of the IEEE Region 10 Conference, 2021

Mitigation Technique against Network Isolation Attack on RPL in 6LoWPAN Network.
Proceedings of the IEEE Region 10 Conference, 2021

DAISS: Design of an Attacker Identification Scheme in CoAP Request/Response Spoofing.
Proceedings of the IEEE Region 10 Conference, 2021

A Fault Diagnosis Technique of SMGFs in $k$-CNOT Based Reversible Circuits.
Proceedings of the IEEE Region 10 Conference, 2021

Conversion of Virtual Lab Experiments using FOSS: A Case Study of Virtual Labs by NMEICT.
Proceedings of the 2021 IEEE International Conference on Engineering, 2021

Selective Fault-Masking for Improving Yield and Performance of On-Chip Networks.
Proceedings of the 2021 IEEE International Conference on Systems, Man, and Cybernetics, 2021

ML for IEEE 802.15. 4e/TSCH: Energy Efficient Approach to Detect DDoS Attack Using Machine Learning.
Proceedings of the 17th International Wireless Communications and Mobile Computing, 2021

LIENE: Lifetime Enhancement for 6LoWPAN Network Using Clustering Approach Use Case: Smart Agriculture.
Proceedings of the Innovations for Community Services - 21st International Conference, 2021

Opacity preserving Countermeasure using Finite State Machines against Differential Scan Attacks.
Proceedings of the 26th IEEE European Test Symposium, 2021

Detection of Stuck-at and Bridging Fault in Reversible Circuits using an Augmented Circuit.
Proceedings of the 30th IEEE Asian Test Symposium, 2021

2020
Formal Modeling of Network-on-Chip Using CFSM and its Application in Detecting Deadlock.
IEEE Trans. Very Large Scale Integr. Syst., 2020

An Efficient Test Set Construction Scheme for Multiple Missing-Gate Faults in Reversible Circuits.
J. Electron. Test., 2020

Approximate Testing of Digital VLSI Circuits using Error Significance based Fault Analysis.
Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020

Adaptive BFS Based Fault Tolerant Routing Algorithm for Network on Chip.
Proceedings of the 2020 IEEE Region 10 Conference, 2020

Maximizing Yield through Retesting of Rejected Circuits using Approximation Technique.
Proceedings of the 2020 IEEE Region 10 Conference, 2020

A Fault Detection Scheme for Reversible Circuits using -Ve Control k-CNOT Based Circuit.
Proceedings of the 2020 IEEE Region 10 Conference, 2020

Test Methodology for Analysis of Coexistent Logic-Level Faults in NoC Channels.
Proceedings of the 2020 IEEE International Conference on Systems, Man, and Cybernetics, 2020

Improving Reliability in Spidergon Network on Chip-Microprocessors.
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

Locating Open-Channels in Octagon Networks on Chip-Microprocessors.
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020

Reliability Monitoring in a Smart NoC Component.
Proceedings of the 27th IEEE International Conference on Electronics, Circuits and Systems, 2020

TA-ACS: A Trust Aware Adaptive Carrier Selection Scheme for Reliable Routing in Delay Tolerant Networks.
Proceedings of the Innovations for Community Services, 2020

SAS: Seasonality Aware Social-Based Forwarder Selection in Delay Tolerant Networks.
Proceedings of the Innovations for Community Services, 2020

BRAIN: Buffer Reservation Attack PreventIoN Using Legitimacy Score in 6LoWPAN Network.
Proceedings of the Innovations for Community Services, 2020

Energy Efficient Approach to Detect Sinkhole Attack Using Roving IDS in 6LoWPAN Network.
Proceedings of the Innovations for Community Services, 2020

Detection and Verification of Decreased Rank Attack using Round-Trip Times in RPL-Based 6LoWPAN Networks.
Proceedings of the 14th IEEE International Conference on Advanced Networks and Telecommunications Systems, 2020

ArsPAN: Attacker Revelation Scheme using Discrete Event System in 6LoWPAN based Buffer Reservation Attack.
Proceedings of the 14th IEEE International Conference on Advanced Networks and Telecommunications Systems, 2020

2019
Performance-Aware Test Scheduling for Diagnosing Coexistent Channel Faults in Topology-Agnostic Networks-on-Chip.
ACM Trans. Design Autom. Electr. Syst., 2019

Supervisory Control Approach and its Symbolic Computation for Power-Aware RT Scheduling.
IEEE Trans. Ind. Informatics, 2019

Energy efficient heuristic application mapping for 2-D mesh-based network-on-chip.
Microprocess. Microsystems, 2019

Discrete event system framework for fault diagnosis with measurement inconsistency: case study of rogue DHCP attack.
IEEE CAA J. Autom. Sinica, 2019

RSBST: an Accelerated Automated Software-Based Self-Test Synthesis for Processor Testing.
J. Electron. Test., 2019

Test Generation for Bridging Faults in Reversible Circuits Using Path-Level Expressions.
J. Electron. Test., 2019

A Binary Decision Diagram Approach to On-line Testing of Asynchronous Circuits with Dynamic and Static C-elements.
J. Electron. Test., 2019

A Low-Cost Test Solution for Reliable Communication in Networks-on-Chip.
J. Electron. Test., 2019

RSBST: A Rapid Software-Based Self-Test Methodology for Processor Testing.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

A Binary Decision Diagram Approach to On-line Testing of Asynchronous Circuits.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

Systematic Design of Approximate Adder Using Significance Based Gate-Level Pruning (SGLP) for Image Processing Application.
Proceedings of the Pattern Recognition and Machine Intelligence, 2019

Evil Twin Attack Detection using Discrete Event Systems in IEEE 802.11 Wi-Fi Networks.
Proceedings of the 27th Mediterranean Conference on Control and Automation, 2019

De-Authentication Attack Detection using Discrete Event Systems in 802.11 Wi-Fi Networks.
Proceedings of the 2019 IEEE International Conference on Advanced Networks and Telecommunications Systems, 2019

LORD: LOw Rate DDoS Attack Detection and Mitigation Using Lightweight Distributed Packet Inspection Agent in IoT Ecosystem.
Proceedings of the 2019 IEEE International Conference on Advanced Networks and Telecommunications Systems, 2019

2018
Reliability-Aware Test Methodology for Detecting Short-Channel Faults in On-Chip Networks.
IEEE Trans. Very Large Scale Integr. Syst., 2018

MATEM: A unified framework based on trust and MCDM for assuring security, reliability and QoS in DTN routing.
J. Netw. Comput. Appl., 2018

On-Line Analysis of Stuck-at Faults in On-Chip Network Interconnects.
J. Circuits Syst. Comput., 2018

A Game Theory Based Multi Layered Intrusion Detection Framework for Wireless Sensor Networks.
Int. J. Wirel. Inf. Networks, 2018

An Efficient Scheme to Detect Evil Twin Rogue Access Point Attack in 802.11 Wi-Fi Networks.
Int. J. Wirel. Inf. Networks, 2018

Design of light weight exact discrete event system diagnosers using measurement limitation: case study of electronic fuel injection system.
Int. J. Syst. Sci., 2018

A game theory based multi layered intrusion detection framework for VANET.
Future Gener. Comput. Syst., 2018

Automation of Test Program Synthesis for Processor Post-silicon Validation.
J. Electron. Test., 2018

Exact Task Completion Time Aware Real-Time Scheduling Based on Supervisory Control Theory of Timed DES.
Proceedings of the 16th European Control Conference, 2018

2017
Fault-Tolerant Preemptive Aperiodic RT Scheduling by Supervisory Control of TDES on Multiprocessors.
ACM Trans. Embed. Comput. Syst., 2017

On-Line Testing of digital VLSI circuits at Register Transfer Level using High Level Decision Diagrams.
Microelectron. J., 2017

Resource optimization for emulation of behavioral models of mixed signal circuits on FPGA: a case study of DC-DC buck converter.
Int. J. Circuit Theory Appl., 2017

Intrusion detection system for PS-Poll DoS attack in 802.11 networks using real time discrete event system.
IEEE CAA J. Autom. Sinica, 2017

A Time-Optimized Scheme Towards Analysis of Channel-Shorts in on-Chip Networks.
J. Electron. Test., 2017

Comments on "Supervisory control for real-time scheduling of periodic and sporadic tasks with resource constraints" [Automatica 45 (2009) 2597-2604].
Autom., 2017

xMAS Based Accurate Modeling and Progress Verification of NoCs.
Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

Charka: A reliability-aware test scheme for diagnosis of channel shorts beyond mesh NoCs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Real-time scheduling of non-preemptive sporadic tasks on uniprocessor systems using Supervisory Control of timed DES.
Proceedings of the 2017 American Control Conference, 2017

2016
False alarm reduction in signature-based IDS: game theory approach.
Secur. Commun. Networks, 2016

Machine learning approach for detection of flooding DoS attacks in 802.11 networks and attacker localization.
Int. J. Mach. Learn. Cybern., 2016

On-line detection and diagnosis of stuck-at faults in channels of NoC-based systems.
Proceedings of the 2016 IEEE International Conference on Systems, Man, and Cybernetics, 2016

A topology-agnostic test model for link shorts in on-chip networks.
Proceedings of the 2016 IEEE International Conference on Systems, Man, and Cybernetics, 2016

One poison is antidote against another poison.
Proceedings of the 2016 IEEE International Conference on Systems, Man, and Cybernetics, 2016

Detecting and diagnosing open faults in NoC channels on activation of diagonal nodes.
Proceedings of the 2016 IEEE International Conference on Systems, Man, and Cybernetics, 2016

Towards a Scalable Test Solution for the Analysis of Interconnect Shorts in On-chip Networks.
Proceedings of the 24th IEEE International Symposium on Modeling, 2016

An on-line test solution for addressing interconnect shorts in on-chip networks.
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

An odd-even scheme to prevent a packet from being corrupted and dropped in fault tolerant NoCs.
Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

When Clustering Shows Optimality towards Analyzing Stuck-at Faults in Channels of On-chip Networks.
Proceedings of the 18th IEEE International Conference on High Performance Computing and Communications; 14th IEEE International Conference on Smart City; 2nd IEEE International Conference on Data Science and Systems, 2016

A Reliability-Aware Topology-Agnostic Test Scheme for Detecting, and Diagnosing Interconnect Shorts in On-chip Networks.
Proceedings of the 18th IEEE International Conference on High Performance Computing and Communications; 14th IEEE International Conference on Smart City; 2nd IEEE International Conference on Data Science and Systems, 2016

Enhancing effectiveness of intrusion detection systems: A hybrid approach.
Proceedings of the 2016 IEEE International Conference on Advanced Networks and Telecommunications Systems, 2016

Enhancing performance of anomaly based intrusion detection systems through dimensionality reduction using principal component analysis.
Proceedings of the 2016 IEEE International Conference on Advanced Networks and Telecommunications Systems, 2016

2015
A Discrete Event System Approach to Online Testing of Speed Independent Circuits.
VLSI Design, 2015

A Binary Decision Diagram based on-line testing of digital VLSI circuits for feedback bridging faults.
Microelectron. J., 2015

A design fix to supervisory control for fault-tolerant scheduling of real-time multiprocessor systems with aperiodic tasks.
Int. J. Control, 2015

Cannibalistic Predator-Prey Model with Disease in Predator - A Delay Model.
Int. J. Bifurc. Chaos, 2015

Advanced Stealth Man-in-The-Middle Attack in WPA2 Encrypted Wi-Fi Networks.
IEEE Commun. Lett., 2015

Real-time embedded systems analysis - From theory to practice.
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

Directed Symbolic Execution for VLSI Circuits.
Proceedings of the 2015 IEEE International Conference on Systems, 2015

An Optimal Diagnosis of NoC Interconnects on Activation of Diagonal Routers.
Proceedings of the 2015 IEEE International Conference on Systems, 2015

Detection of De-Authentication DoS Attacks in Wi-Fi Networks: A Machine Learning Approach.
Proceedings of the 2015 IEEE International Conference on Systems, 2015

Timed Discrete event system approach to online testing of asynchronous circuits.
Proceedings of the 23rd Mediterranean Conference on Control and Automation, 2015

A packet address driven test strategy for stuck-at faults in networks-on-chip interconnects.
Proceedings of the 23rd Mediterranean Conference on Control and Automation, 2015

I<sup>2</sup>-diagnosability framework for detection of Advanced Stealth Man in the Middle attack in Wi-Fi networks.
Proceedings of the 23rd Mediterranean Conference on Control and Automation, 2015

Reliability on Top of Best Effort Delivery: Maximal Connectivity Test on NoC Interconnects.
Proceedings of the 8th Annual ACM India Conference, Ghaziabad, India, October 29-31, 2015, 2015

Adaptive path selection for high throughput Heterogeneous Wireless Mesh Networks.
Proceedings of the 2015 IEEE International Conference on Advanced Networks and Telecommuncations Systems, 2015

2014
Diagnosability in stochastic Petri Net based DES models.
Proceedings of the 22nd Mediterranean Conference on Control and Automation, 2014

M-HRP for Wireless Mesh Networks and its performance evaluation.
Proceedings of the Sixth International Conference on Communication Systems and Networks, 2014

Detection of faulty interswitch links in 2-D mesh network-on-chips.
Proceedings of the 2014 IEEE International Conference on Advanced Networks and Telecommuncations Systems, 2014

2013
Towards reducing false alarms in network intrusion detection systems with data summarization technique.
Secur. Commun. Networks, 2013

An Active Host-Based Intrusion Detection System for ARP-Related Attacks and its Verification.
CoRR, 2013

Equivalence of Fair Diagnosability and Stochastic Diagnosability of Discrete Event Systems.
Proceedings of the IEEE International Conference on Systems, 2013

2012
Diagnosability of discrete event systems for temporary failures.
Comput. Electr. Eng., 2012

An Active Detection Mechanism for Detecting ICMP Based Attacks.
Proceedings of the 11th IEEE International Conference on Trust, 2012

Detection and Mitigation of Induced Low Rate TCP-Targeted Denial of Service Attack.
Proceedings of the Sixth International Conference on Software Security and Reliability, 2012

Detection of NDP based attacks using MLD.
Proceedings of the 5th International Conference of Security of Information and Networks, 2012

2011
Network specific false alarm reduction in intrusion detection system.
Secur. Commun. Networks, 2011

An active DES based IDS for ARP spoofing.
Proceedings of the IEEE International Conference on Systems, 2011

Detection of neighbor solicitation and advertisement spoofing in IPv6 neighbor discovery protocol.
Proceedings of the 4th International Conference on Security of Information and Networks, 2011

Research and application of One-class small hypersphere support vector machine for network anomaly detection.
Proceedings of the Third International Conference on Communication Systems and Networks, 2011

Sequencegram: n-gram modeling of system calls for program based anomaly detection.
Proceedings of the Third International Conference on Communication Systems and Networks, 2011

A host based DES approach for detecting ARP spoofing.
Proceedings of the 2011 IEEE Symposium on Computational Intelligence in Cyber Security, 2011

E-AODV for Wireless Mesh Networks and Its Performance Evaluation.
Proceedings of the 2011 International Conference on Broadband, 2011

2010
Diagnosability of delay-deadline failures in fair real time discrete event models.
Int. J. Syst. Sci., 2010

Fairness of Transitions in Diagnosability of Discrete Event Systems.
Discret. Event Dyn. Syst., 2010

A BDD-based approach to design power-aware on-line detectors for digital circuits.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010

An Active Intrusion Detection System for LAN Specific Attacks.
Proceedings of the Advances in Computer Science and Information Technology, 2010

Distance Based Fast Hierarchical Clustering Method for Large Datasets.
Proceedings of the Rough Sets and Current Trends in Computing, 2010

Peer-to-Peer Network Classification Using nu-Maximal Margin Spherical Structured Multiclass Support Vector Machine.
Proceedings of the Data Engineering and Management - Second International Conference, 2010

Fair diagnosability in PN-based DES models.
Proceedings of the 8th IEEE International Conference on Control and Automation, 2010

FPGA based chip emulation system for test development and verification of analog and mixed signal circuits (abstract only).
Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, 2010

Layered Higher Order N-grams for Hardening Payload Based Anomaly Intrusion Detection.
Proceedings of the ARES 2010, 2010

2008
Unified Technique for on-Line Testing of Digital Circuits: Delay and Stuck-at Fault Models.
J. Circuits Syst. Comput., 2008

Macromodel Based Fault Simulation of Linear Circuits using Parameter Estimation.
Proceedings of the IEEE Reglon 10 Colloquium and Third International Conference on Industrial and Information Systems, 2008

2006
Concurrent Testing of Digital Circuits for Non-Classical Fault Models: Bridging Faults and n-Detect Test.
Proceedings of the 7th Latin American Test Workshop, 2006

Concurrent Testing of Digital Circuits for Advanced Fault Models.
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

Fairness of transitions in diagnosability analysis of hybrid systems.
Proceedings of the American Control Conference, 2006

2005
A Formal Approach to On-Line Monitoring of Digital VLSI Circuits: Theory, Design and Implementation.
J. Electron. Test., 2005

On-Line Testing of Digital Circuits for n-Detect and Bridging Fault Models.
Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005

2004
A discrete event systems approach to online testing of digital VLSI circuits.
Proceedings of the IEEE International Conference on Systems, 2004

Optimization of the Theory of FDD of DES for Alleviation of the State Explosion Problem and Development of CAD Tools for On-line Testing of Digital VLSI Circuits.
Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004

A BIST Approach to On-Line Monitoring of Digital VLSI Circuits: A CAD Tool.
Proceedings of the 13th Asian Test Symposium (ATS 2004), 2004


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