Rahul Bodduna

Orcid: 0000-0003-2098-2606

According to our database1, Rahul Bodduna authored at least 3 papers between 2016 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2020
Brutus: Refuting the Security Claims of the Cache Timing Randomization Countermeasure Proposed in CEASER.
IEEE Comput. Archit. Lett., 2020

PARAM: A Microprocessor Hardened for Power Side-Channel Attack Resistance.
Proceedings of the 2020 IEEE International Symposium on Hardware Oriented Security and Trust, 2020

2016
SHAKTI Processors: An Open-Source Hardware Initiative.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016


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