Rajat Arora

Affiliations:
  • Cadence Design Systems, San Jose, CA, USA
  • Virginia Technology, Department of Electrical and Computer Engineering, Blacksburg, VA, USA


According to our database1, Rajat Arora authored at least 5 papers between 2003 and 2005.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2005
Extended Forward Implications and Dual Recurrence Relations to Identify Sequentially Untestable Faults.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

2004
Using Global Structural Relationships of Signals to Accelerate SAT-based Combinational Equivalence Checking.
J. Univers. Comput. Sci., 2004

Enhancing SAT-based Bounded Model Checking using Sequential Logic Implications.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

CNF formula simplification using implication reasoning.
Proceedings of the Ninth IEEE International High-Level Design Validation and Test Workshop 2004, 2004

2003
Enhancing SAT-based equivalence checking with static logic implications.
Proceedings of the Eighth IEEE International High-Level Design Validation and Test Workshop 2003, 2003


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