Rajeev K. Nain

According to our database, Rajeev K. Nain authored at least 8 papers between 2008 and 2013.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of five.

2013

Fast floorplanning with placement constraints.

Shantesh Pinge, Rajeev K. Nain, Malgorzata Chrzanowska-Jeske

Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013

2012

Performance analysis of CNFET based circuits in the presence of fabrication imperfections.

Malgorzata Chrzanowska-Jeske, Rehman Ashraf, Rajeev K. Nain, Siva G. Narendra

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011

Fast Placement-Aware 3-D Floorplanning Using Vertical Constraints on Sequence Pairs.

Rajeev K. Nain, Malgorzata Chrzanowska-Jeske

IEEE Trans. Very Large Scale Integr. Syst., 2011

2010

Design methodology for Carbon Nanotube based circuits in the presence of metallic tubes.

Rehman Ashraf, Rajeev K. Nain, Malgorzata Chrzanowska-Jeske, Siva G. Narendra

Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, 2010

Yield improvement of 3D ICs in the presence of defects in through signal vias.

Rajeev K. Nain, Shantesh Pinge, Malgorzata Chrzanowska-Jeske

Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Yield enhancement by tube redundancy in CNFET-based circuits.

Rehman Ashraf, Rajeev K. Nain, Malgorzata Chrzanowska-Jeske, Siva G. Narendra

Proceedings of the 17th IEEE International Conference on Electronics, 2010

2009

Placement-aware 3D Floorplanning.

Rajeev K. Nain, Malgorzata Chrzanowska-Jeske

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

2008

Rectangular 3D wirelength distribution models.

Rajeev K. Nain, Rajarshi Ray, Malgorzata Chrzanowska-Jeske

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008