Siva G. Narendra
Affiliations:- Tyfone Inc., Portland, OR, USA
- Portland State University, Department of Electrical and Computer Engineering, OR, USA
- Intel Corporation, Microprocessor Research Laboratory, Hillsboro, OR, USA
According to our database1,
Siva G. Narendra
authored at least 45 papers
between 1998 and 2012.
Collaborative distances:
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Bibliography
2012
Performance analysis of CNFET based circuits in the presence of fabrication imperfections.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012
2010
Design methodology for Carbon Nanotube based circuits in the presence of metallic tubes.
Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, 2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Proceedings of the 17th IEEE International Conference on Electronics, 2010
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010
2008
Introduction to the Special Issue on the 2007 IEEE International Solid-State Circuits Conference.
IEEE J. Solid State Circuits, 2008
Power Systems from the Gigawatt to the Microwatt - Generation, Distribution, Storage and Efficient Use of Energy (Forum).
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
2007
Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
2005
Microelectron. J., 2005
A 233-MHz 80%-87% efficient four-phase DC-DC converter utilizing air-core inductors on package.
IEEE J. Solid State Circuits, 2005
ACM J. Emerg. Technol. Comput. Syst., 2005
Adaptive circuit techniques to minimize variation impacts on microprocessor performance and power.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Cascode buffer for monolithic voltage conversion operating at high input supply voltages.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
2004
IEEE Trans. Circuits Syst. II Express Briefs, 2004
Full-chip subthreshold leakage power prediction and reduction techniques for sub-0.18-μm CMOS.
IEEE J. Solid State Circuits, 2004
Measurements and analysis of SER-tolerant latch in a 90-nm dual-V<sub>T</sub> CMOS process.
IEEE J. Solid State Circuits, 2004
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004
The Influence of Process Variations on the Halo MOSFETs and its Implications on the Analog Circuit performance.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004
High Input Voltage Step-Down DC-DC Converters for Integration in a Low Voltage CMOS Process.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004
Feasibility of monolithic and 3D-stacked DC-DC converters for microprocessors in 90nm technology generation.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004
Proceedings of the 41th Design Automation Conference, 2004
2003
Analysis of buck converters for on-chip integration with a dual supply voltage microprocessor.
IEEE Trans. Very Large Scale Integr. Syst., 2003
Dynamic sleep transistor and body bias for active leakage power control of microprocessors.
IEEE J. Solid State Circuits, 2003
Effectiveness of adaptive supply voltage and body bias for reducing impact of parameter variations in low power and high performance microprocessors.
IEEE J. Solid State Circuits, 2003
IEEE J. Solid State Circuits, 2003
IEEE J. Solid State Circuits, 2003
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003
Temperature and process invariant MOS-based reference current generation circuits for sub-1V operation.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003
Proceedings of the 40th Design Automation Conference, 2003
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003
2002
Effect of Metal oxide semiconductor field-effect transistors threshold voltage variation on high-performance circuits.
PhD thesis, 2002
Analysis of dual-V<sub>T</sub> SRAM cells with full-swing single-ended bit line sensing for on-chip cache.
IEEE Trans. Very Large Scale Integr. Syst., 2002
IEEE J. Solid State Circuits, 2002
Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage.
IEEE J. Solid State Circuits, 2002
IEEE Des. Test Comput., 2002
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002
2001
Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001
1999
Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC's.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999
1998
Proceedings of the 35th Conference on Design Automation, 1998