Rajendra Kumar Nagaria
According to our database1,
Rajendra Kumar Nagaria
authored at least 22 papers
between 2009 and 2023.
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Bibliography
2023
Comput. Networks, May, 2023
Integr., March, 2023
2022
A Novel Method to Control Leakage and Noise in Domino Circuit for Wide Fan-In OR Logic.
J. Circuits Syst. Comput., 2022
2021
Design and Performance of High-Speed Energy-Efficient CMOS Double Tail Dynamic Latch Comparator Using GACOBA Load Suitable for Low Voltage Applications.
J. Circuits Syst. Comput., 2021
Open Comput. Sci., 2021
2020
3D geographical routing protocols in wireless ad hoc and sensor networks: an overview.
Wirel. Networks, 2020
A Sub-1 V nanopower subthreshold current and voltage reference using current subtraction technique and cascoded active load.
Integr., 2020
Proceedings of the 9th International Conference on Software and Computer Applications, 2020
2019
J. Circuits Syst. Comput., 2019
Design and Analysis of an Energy-Efficient High-Speed CMOS Double-Tail Dynamic Comparator with Reduced Kickback Noise Effect.
J. Circuits Syst. Comput., 2019
Proceedings of the 58th Annual Conference of the Society of Instrument and Control Engineers of Japan, 2019
2018
Energy efficient neoteric design of a 3-input Majority Gate with its implementation and physical proof in Quantum dot Cellular Automata.
Nano Commun. Networks, 2018
Optimization for offset and kickback-noise in novel CMOS double-tail dynamic comparator: A low-power, high-speed design approach using bulk-driven load.
Microelectron. J., 2018
Enhanced Gain Low-Power CMOS Amplifiers: A Novel Design Approach Using Bulk-Driven Load and Introduction to GACOBA Technique.
J. Circuits Syst. Comput., 2018
A new leakage-tolerant high speed comparator based domino gate for wide fan-in OR logic for low power VLSI circuits.
Integr., 2018
2017
J. Low Power Electron., 2017
2016
An Innovative Low Power Full Adder Design in Nano Technology Based Quantum Dot Cellular Automata.
J. Low Power Electron., 2016
2015
A Review on Robust Low Power System Level Digital Circuit Design Approaches in Nano-CMOS Technologies.
Proceedings of the Sixth International Conference on Computer and Communication Technology 2015, 2015
2013
VLSI Design, 2013
2012
Performance Analysis of High Speed Hybrid CMOS Full Adder Circuits for Low Voltage VLSI Design.
VLSI Design, 2012
2010
On the New Design of sinusoid voltage Controlled oscillators Using Multiplier in CFA-Based Double Integrator Loop.
J. Circuits Syst. Comput., 2010
2009
PAPR Reduction for OFDM Scheme by New Partial Transmit Sequence Technique in Wireless Communication Systems.
Proceedings of the First International Conference on Computational Intelligence, 2009