Rajesh J. S.

According to our database1, Rajesh J. S. authored at least 10 papers between 2015 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2019
Energy Efficient Network-on-Chip Architectures for Many-Core Near-Threshold Computing System.
J. Low Power Electron., 2019

Securing Data Center Against Power Attacks.
J. Hardw. Syst. Secur., 2019

Probabilistic Verification for Reliable Network-on-Chip System Design.
Proceedings of the Formal Methods for Industrial Critical Systems, 2019

2017
IcoNoClast: Tackling Voltage Noise in the NoC Power Supply Through Flow-Control and Routing Algorithms.
IEEE Trans. Very Large Scale Integr. Syst., 2017

Security Measures Against a Rogue Network-on-Chip.
J. Hardw. Syst. Secur., 2017

2016
BoostNoC: power efficient network-on-chip architecture for near threshold computing.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

PRADA: Combating voltage noise in the NoC power supply through flow-control and routing algorithms.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Catching the flu: emerging threats from a third party power management unit.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2015
Runtime Detection of a Bandwidth Denial Attack from a Rogue Network-on-Chip.
Proceedings of the 9th International Symposium on Networks-on-Chip, 2015

Tackling voltage emergencies in NoC through timing error resilience.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015


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