Sanghamitra Roy

According to our database1, Sanghamitra Roy authored at least 77 papers between 2003 and 2020.

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Bibliography

2020
Exploring Warp Criticality in Near-Threshold GPGPU Applications Using a Dynamic Choke Point Analysis.
IEEE Trans. Very Large Scale Integr. Syst., 2020

GreenTPU: Predictive Design Paradigm for Improving Timing Error Resilience of a Near-Threshold Tensor Processing Unit.
IEEE Trans. Very Large Scale Integr. Syst., 2020

EFFORT: Enhancing Energy Efficiency and Error Resilience of a Near-Threshold Tensor Processing Unit.
Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019
Energy Efficient Network-on-Chip Architectures for Many-Core Near-Threshold Computing System.
J. Low Power Electron., 2019

Securing Data Center Against Power Attacks.
J. Hardw. Syst. Secur., 2019

Probabilistic Verification for Reliable Network-on-Chip System Design.
Proceedings of the Formal Methods for Industrial Critical Systems, 2019

Predicting Critical Warps in Near-Threshold GPGPU Applications using a Dynamic Choke Point Analysis.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

GreenTPU: Improving Timing Error Resilience of a Near-Threshold Tensor Processing Unit.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018
Dynamic Choke Sensing for Timing Error Resilience in NTC Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2018

Trident: Comprehensive Choke Error Mitigation in NTC Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2018

TASPDetect: Reviving Trust in 3PIP By Detecting TASP Trojans.
Microprocess. Microsystems, 2018

FIFA: Exploring a Focally Induced Fault Attack Strategy in Near-Threshold Computing.
IEEE Embed. Syst. Lett., 2018

ACE-GPU: Tackling Choke Point Induced Performance Bottlenecks in a Near-Threshold Computing GPU.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018

Reliability and Uniformity Enhancement in 8T-SRAM based PUFs operating at NTC.
Proceedings of the International Symposium on Low Power Electronics and Design, 2018

Trident: A comprehensive timing error resilient technique against choke points at NTC.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

2017
IcoNoClast: Tackling Voltage Noise in the NoC Power Supply Through Flow-Control and Routing Algorithms.
IEEE Trans. Very Large Scale Integr. Syst., 2017

SSAGA: SMs Synthesized for Asymmetric GPGPU Applications.
ACM Trans. Design Autom. Electr. Syst., 2017

Split Latency Allocator: Process Variation-Aware Register Access Latency Boost in a Near-Threshold Graphics Processing Unit.
J. Low Power Electron., 2017

Security Measures Against a Rogue Network-on-Chip.
J. Hardw. Syst. Secur., 2017

Revamping timing error resilience to tackle choke points at NTC systems.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
BoostNoC: power efficient network-on-chip architecture for near threshold computing.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

PRADA: Combating voltage noise in the NoC power supply through flow-control and routing algorithms.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Synergistic timing speculation for multi-threaded programs.
Proceedings of the 53rd Annual Design Automation Conference, 2016

Catching the flu: emerging threats from a third party power management unit.
Proceedings of the 53rd Annual Design Automation Conference, 2016

SwiftGPU: fostering energy efficiency in a near-threshold GPU through a tactical performance boost.
Proceedings of the 53rd Annual Design Automation Conference, 2016

2015
Wearout Resilience in NoCs Through an Aging Aware Adaptive Routing Algorithm.
IEEE Trans. Very Large Scale Integr. Syst., 2015

DARP-MP: Dynamically Adaptable Resilient Pipeline Design in Multicore Processors.
ACM Trans. Design Autom. Electr. Syst., 2015

Resilient Cache Design for Mobile Processors in the Near-Threshold Regime.
J. Low Power Electron., 2015

Runtime Detection of a Bandwidth Denial Attack from a Rogue Network-on-Chip.
Proceedings of the 9th International Symposium on Networks-on-Chip, 2015

Tackling voltage emergencies in NoC through timing error resilience.
Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2015

Opportunistic turbo execution in NTC: exploiting the paradigm shift in performance bottlenecks.
Proceedings of the 52nd Annual Design Automation Conference, 2015

2014
Exploring High-Throughput Computing Paradigm for Global Routing.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Dark Silicon Aware Multicore Systems: Employing Design Automation With Architectural Insight.
IEEE Trans. Very Large Scale Integr. Syst., 2014

Exploiting static and dynamic locality of timing errors in robust L1 cache design.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

DARP: Dynamically Adaptable Resilient Pipeline design in microprocessors.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Fort-NoCs: Mitigating the Threat of a Compromised NoC.
Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Tackling QoS-induced aging in exascale systems through agile path selection.
Proceedings of the 2014 International Conference on Hardware/Software Codesign and System Synthesis, 2014

2013
Architecturally Homogeneous Power-Performance Heterogeneous Multicore Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2013

Using Adaptive Body Biasing for Robust Process Variation Aware DRAM Design.
J. Low Power Electron., 2013

A global router on GPU architecture.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

Long term sustainability of differentially reliable systems in the dark silicon era.
Proceedings of the 2013 IEEE 31st International Conference on Computer Design, 2013

Proactive aging management in heterogeneous NoCs through a criticality-driven routing approach.
Proceedings of the Design, Automation and Test in Europe, 2013

Efficiently tolerating timing violations in pipelined microprocessors.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

HCI-tolerant NoC router microarchitecture.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

DMR3D: dynamic memory relocation in 3D multicore systems.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

2012
Stack Aware Threshold Voltage Assignment in 3-D Multicore Designs.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Analysis of intermittent timing fault vulnerability.
Microelectron. Reliab., 2012

Process variation aware DRAM design using block based adaptive body biasing algorithm.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Power-Performance Yield optimization for MPSoCs using MILP.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Designing for dark silicon: a methodological perspective on energy efficient systems.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Mitigating NBTI in the physical register file through stress prediction.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

DOC: Fast and accurate congestion analysis for global routing.
Proceedings of the 30th International IEEE Conference on Computer Design, 2012

An MILP-based aging-aware routing algorithm for NoCs.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Predicting timing violations through instruction-level path sensitization analysis.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Towards graceful aging degradation in NoCs through an adaptive routing algorithm.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2011
Design and Implementation of a Throughput-Optimized GPU Floorplanning Algorithm.
ACM Trans. Design Autom. Electr. Syst., 2011

Exploiting dynamic micro-architecture usage in gate sizing.
Microprocess. Microsystems, 2011

Microprocessor Power Supply Noise Aware Floorplanning Using a Circuit-Architectural Framework.
J. Low Power Electron., 2011

A GPU Algorithm for IC Floorplanning: Specification, Analysis and Optimization.
Proceedings of the VLSI Design 2011: 24th International Conference on VLSI Design, 2011

Integrated circuit-architectural framework for PSN aware floorplanning in microprocessors.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Analysis and mitigation of NBTI aging in register file: An end-to-end approach.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Optimizing simulated annealing on GPU: A case study with IC floorplanning.
Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Topologically homogeneous power-performance heterogeneous multicore systems.
Proceedings of the Design, Automation and Test in Europe, 2011

2010
A Novel Threshold Voltage Assignment for 3D Multicore Designs.
J. Low Power Electron., 2010

Rethinking Threshold Voltage Assignment in 3D Multicore Designs.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

A convex optimization framework for leakage aware thermal provisioning in 3D multicore architectures.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Microarchitecture aware gate sizing: A framework for circuit-architecture co-optimization.
Proceedings of the 28th International Conference on Computer Design, 2010

2008
Wire Sizing.
Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

An optimal algorithm for sizing sequential circuits for industrial library based designs.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
Numerically Convex Forms and Their Application in Gate Sizing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

SmartSmooth: A linear time convexity preserving smoothing algorithm for numerically convex data with application to VLSI design.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
ConvexSmooth: A simultaneous convex fitting and smoothing algorithm for convex optimization problems.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

2005
An Algorithm for Trading Off Quantization Error with Hardware Resources for MATLAB-Based FPGA Design.
IEEE Trans. Computers, 2005

ConvexFit: an optimal minimum-error convex fitting and smoothing algorithm with application to gate-sizing.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

2004
An algorithm for trading off quantization error with hardware resources for MATLAB based FPGA design.
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004

An algorithm for converting floating-point computations to fixed-point in MATLAB based FPGA design.
Proceedings of the 41th Design Automation Conference, 2004

2003
Hierarchical representation of digitized curves through dominant point detection.
Pattern Recognit. Lett., 2003


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