Ralf Wollowski

Affiliations:
  • Hasso Plattner Institute, Potsdam, Germany
  • University of Kaiserslautern, Department of Electrical Engineering, Germany


According to our database1, Ralf Wollowski authored at least 14 papers between 1992 and 2017.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2017
Data path optimisation and delay matching for asynchronous bundled-data balsa circuits.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

2016
Optimising Bundled-Data Balsa Circuits.
Proceedings of the 22nd IEEE International Symposium on Asynchronous Circuits and Systems, 2016

2011
Signal transition graph decomposition: internal communication for speed independent circuit implementation.
IET Comput. Digit. Tech., 2011

STG Decomposition: Partitioning Heuristics.
Proceedings of the 11th International Conference on Application of Concurrency to System Design, 2011

2010
STG Decomposition: Internal Communication for SI Implementability.
Proceedings of the 10th International Conference on Application of Concurrency to System Design, 2010

2009
Avoiding Irreducible CSC Conflicts by Internal Communication.
Fundam. Informaticae, 2009

STG decomposition strategies in combination with unfolding.
Acta Informatica, 2009

DESIJ--Enabling Decomposition-Based Synthesis of Complex Asynchronous Controllers.
Proceedings of the Ninth International Conference on Application of Concurrency to System Design, 2009

2006
Strategies for Optimised STG Decomposition.
Proceedings of the Sixth International Conference on Application of Concurrency to System Design (ACSD 2006), 2006

2002
Decomposition in Asynchronous Circuit Design.
Proceedings of the Concurrency and Hardware Design, Advances in Petri Nets, 2002

2000
CASCADE: A Tool Kernel Supporting a Comprehensive Design Method for Asynchronous Controllers.
Proceedings of the Application and Theory of Petri Nets 2000, 2000

1999
From STG to Extended-Burst-Mode Machines.
Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '99), 1999

1997
Entwurfsorientierte Petrinetz-Modellierung des Schnittstellen-Sollverhaltens asynchroner Schaltwerksverbünde.
PhD thesis, 1997

1992
Controller Implementation by Communicating Asynchronous Sequential Circuits Generated from a Petri Net Specification of Required Behavior.
Proceedings of the Synthesis for Control Dominated Circuits, 1992


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