Victor Khomenko

According to our database1, Victor Khomenko
  • authored at least 60 papers between 1999 and 2017.
  • has a "Dijkstra number"2 of four.

Timeline

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Bibliography

2017
Benefits of asynchronous control for analog electronics: Multiphase buck case study.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
A fixed window Level Crossing ADC with activity dependent power dissipation.
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016

2015
Modelling and Analysis Mobile Systems Using \pi -calculus (EFCP).
Trans. Petri Nets and Other Models of Concurrency, 2015

Factored Planning: From Automata to Petri Nets.
ACM Trans. Embedded Comput. Syst., 2015

Diagnosability under Weak Fairness.
ACM Trans. Embedded Comput. Syst., 2015

Design and Verification of Speed-Independent Multiphase Buck Controller.
Proceedings of the 21st IEEE International Symposium on Asynchronous Circuits and Systems, 2015

Opportunistic Merge Element.
Proceedings of the 21st IEEE International Symposium on Asynchronous Circuits and Systems, 2015

2014
Algebra of Parameterised Graphs.
ACM Trans. Embedded Comput. Syst., 2014

Recent advances in unfolding technique.
Theor. Comput. Sci., 2014

Direct Construction of Complete Merged Processes.
Comput. J., 2014

Diagnosability under Weak Fairness.
Proceedings of the 14th International Conference on Application of Concurrency to System Design, 2014

2013
A Polynomial Translation of pi-calculus FCPs to Safe Petri Nets.
Logical Methods in Computer Science, 2013

Contextual Merged Processes.
Proceedings of the Application and Theory of Petri Nets and Concurrency, 2013

Factored Planning: From Automata to Petri Nets.
Proceedings of the 13th International Conference on Application of Concurrency to System Design, 2013

2012
A Polynomial Translation of π-Calculus (FCP) to Safe Petri Nets.
Proceedings of the CONCUR 2012 - Concurrency Theory - 23rd International Conference, 2012

On Dual-Rail Control Logic for Enhanced Circuit Robustness.
Proceedings of the 12th International Conference on Application of Concurrency to System Design, 2012

Algebra of Parameterised Graphs.
Proceedings of the 12th International Conference on Application of Concurrency to System Design, 2012

2011
Flat Arbiters.
Fundam. Inform., 2011

Logic Decomposition of Asynchronous Circuits Using STG Unfoldings.
Proceedings of the 17th IEEE International Symposium on Asynchronous Circuits and Systems, 2011

An Algorithm for Direct Construction of Complete Merged Processes.
Proceedings of the Applications and Theory of Petri Nets - 32nd International Conference, 2011

Unfolding Models of Asynchronous Systems: Applications to Analysis and Synthesis.
Proceedings of the International Workshop on Petri Nets and Software Engineering, 2011

Improved Parallel Composition of Labelled Petri Nets.
Proceedings of the 11th International Conference on Application of Concurrency to System Design, 2011

2010
A New Type of Behaviour-Preserving Transition Insertions in Unfolding Prefixes.
Proceedings of the Graph Transformations - 5th International Conference, 2010

2009
Efficient Automatic Resolution of Encoding Conflicts Using STG Unfoldings.
IEEE Trans. VLSI Syst., 2009

A Practical Approach to Verification of Mobile Systems Using Net Unfoldings.
Fundam. Inform., 2009

A Case for Using Signal Transition Graphs for Analysing and Refining Genetic Networks.
Electr. Notes Theor. Comput. Sci., 2009

STG decomposition strategies in combination with unfolding.
Acta Inf., 2009

Workcraft - A Framework for Interpreted Graph Models.
Proceedings of the Applications and Theory of Petri Nets, 2009

Flat Arbiters.
Proceedings of the Ninth International Conference on Application of Concurrency to System Design, 2009

Checking pi-Calculus Structural Congruence is Graph Isomorphism Complete.
Proceedings of the Ninth International Conference on Application of Concurrency to System Design, 2009

2008
Output-Determinacy and Asynchronous Circuit Synthesis.
Fundam. Inform., 2008

Resolution of Encoding Conflicts by Signal Insertion and Concurrency Reduction Based on STG Unfoldings.
Fundam. Inform., 2008

Derivation of Monotonic Covers for Standard-C Implementation Using STG Unfoldings.
Proceedings of the 14th IEEE International Symposium on Asynchronous Circuits and Systems, 2008

A Practical Approach to Verification of Mobile Systems Using Net Unfoldings.
Proceedings of the Applications and Theory of Petri Nets, 29th International Conference, 2008

2007
On the well-foundedness of adequate orders used for construction of complete unfolding prefixes.
Inf. Process. Lett., 2007

Verification of bounded Petri nets using integer programming.
Formal Methods in System Design, 2007

Combining Decomposition and Unfolding for STG Synthesis.
Proceedings of the Petri Nets and Other Models of Concurrency, 2007

Behaviour-Preserving Transition Insertions in Unfolding Prefixes.
Proceedings of the Petri Nets and Other Models of Concurrency, 2007

Output-Determinacy and Asynchronous Circuit Synthesis.
Proceedings of the Seventh International Conference on Application of Concurrency to System Design (ACSD 2007), 2007

Efficient Automatic Resolution of Encoding Conflicts Using STG Unfoldings.
Proceedings of the Seventh International Conference on Application of Concurrency to System Design (ACSD 2007), 2007

2006
Logic Synthesis for Asynchronous Circuits Based on STG Unfoldings and Incremental SAT.
Fundam. Inform., 2006

Merged processes: a new condensed representation of Petri net behaviour.
Acta Inf., 2006

On Specification and Verification of Location-Based Fault Tolerant Mobile Systems.
Proceedings of the Rigorous Development of Complex Fault-Tolerant Systems [FP6 IST-511599 RODIN project], 2006

Strategies for Optimised STG Decomposition.
Proceedings of the Sixth International Conference on Application of Concurrency to System Design (ACSD 2006), 2006

Resolution of Encoding Conflicts by Signal Insertion and Concurrency Reduction Based on STG Unfoldings.
Proceedings of the Sixth International Conference on Application of Concurrency to System Design (ACSD 2006), 2006

2005
Merged Processes - A New Condensed Representation of Petri Net Behaviour.
Proceedings of the CONCUR 2005 - Concurrency Theory, 16th International Conference, 2005

2004
Detecting State Encoding Conflicts in STG Unfoldings Using SAT.
Fundam. Inform., 2004

Parallel LTL-X Model Checking of High-Level Petri Nets Based on Unfoldings.
Proceedings of the Computer Aided Verification, 16th International Conference, 2004

Logic Synthesis for Asynchronous Circuits Based on Petri Net Unfoldings and Incremental SAT.
Proceedings of the 4th International Conference on Application of Concurrency to System Design (ACSD 2004), 2004

2003
Canonical prefixes of Petri net unfoldings.
Acta Inf., 2003

Branching Processes of High-Level Petri Nets.
Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2003

Visualization and Resolution of Coding Conflicts in Asynchronous Circuit Design.
Proceedings of the 2003 Design, 2003

Detecting State Coding Conflicts in STG Unfoldings Using SAT.
Proceedings of the 3rd International Conference on Application of Concurrency to System Design (ACSD 2003), 2003

Synthesis of Asynchronous Hardware from Petri Nets.
Proceedings of the Lectures on Concurrency and Petri Nets, 2003

2002
Parallelisation of the Petri Net Unfolding Algorithm.
Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2002

Detecting State Coding Conflicts in STGs Using Integer Programming.
Proceedings of the 2002 Design, 2002

Canonical Prefixes of Petri Net Unfoldings.
Proceedings of the Computer Aided Verification, 14th International Conference, 2002

2001
Towards an Efficient Algorithm for Unfolding Petri Nets.
Proceedings of the CONCUR 2001, 2001

2000
LP Deadlock Checking Using Partial Order Dependencies.
Proceedings of the CONCUR 2000, 2000

1999
The development of interactive algorithms for the Mathematical Environment.
Electr. Notes Theor. Comput. Sci., 1999


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