Ramesh Bhakthavatchalu

According to our database, Ramesh Bhakthavatchalu authored at least 3 papers between 2014 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2025

Scalable FPGA Implementation of a Reliability-Based Direct Turbo Decoder for Short Block Codes.

Senthil Murugan, Ramesh Bhakthavatchalu, Karthi Balasubramanian, B. Yamuna, Deepak Mishra, Sree Ranjani Rajendran

IEEE Access, 2025

2019

Comparative Study of Test Pattern Generation Systems to Reduce Test Application Time.

Patare Snehal Dilip, Geethu Remadevi Somanathan, Ramesh Bhakthavatchalu

Proceedings of the 9th International Symposium on Embedded Computing and System Design, 2019

2014

Deterministic seed selection and pattern reduction in Logic BIST.

Ramesh Bhakthavatchalu, Sreeja Krishnan, V. Vineeth, M. Nirmala Devi

Proceedings of the 18th International Symposium on VLSI Design and Test, 2014