Sree Ranjani Rajendran

Orcid: 0000-0002-7884-4049

According to our database1, Sree Ranjani Rajendran authored at least 10 papers between 2017 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

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Bibliography

2024
CAD Tools Pathway in Hardware Security.
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024

2023
Benchmarking of SoC-Level Hardware Vulnerabilities: A Complete Walkthrough.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023

HUnTer: Hardware Underneath Trigger for Exploiting SoC-level Vulnerabilities.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022
A comprehensive survey of physical and logic testing techniques for Hardware Trojan detection and prevention.
J. Cryptogr. Eng., 2022

Adiabatic Physical Unclonable Function Using Cross-Coupled Pair.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022

2020
KARNA for a Trustable Hardware.
Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020

SoK: Physical and Logic Testing Techniques for Hardware Trojan Detection.
Proceedings of the 4th ACM Workshop on Attacks and Solutions in Hardware Security Workshop, 2020

2018
Enhanced Logical Locking for a Secured Hardware IP Against Key-Guessing Attacks.
Proceedings of the VLSI Design and Test - 22nd International Symposium, 2018

A Novel Logical Locking Technique Against Key-Guessing Attacks.
Proceedings of the 8th International Symposium on Embedded Computing and System Design, 2018

2017
A Flexible Online Checking Technique to Enhance Hardware Trojan Horse Detectability by Reliability Analysis.
IEEE Trans. Emerg. Top. Comput., 2017


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