Rasika Dhavse

According to our database, Rasika Dhavse authored at least 6 papers between 2010 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

ASIC implementation of ECG denoising FIR filter by using hybrid Vedic-Wallace tree multiplier.

Sudhanshu Janwadkar, Rasika Dhavse

Int. J. Circuit Theory Appl., April, 2024

ASIC design of power and area efficient programmable FIR filter using optimized Urdhva-Tiryagbhyam Multiplier for impedance cardiography.

Sudhanshu Janwadkar, Rasika Dhavse

Microprocess. Microsystems, 2024

2022

Investigation and Analysis of Power Performance Area (PPA) Cards of Digital Multiplier Architectures.

Sudhanshu Janwadkar, Rasika Dhavse

J. Circuits Syst. Comput., 2022

2020

Implementation and Performance Evaluation of Novel Line Adder Architecture for Portable Systems : A Vedic Mathematics Approach.

Sudhanshu Janwadkar, Rasika Dhavse

Proceedings of the 2020 IEEE Region 10 Conference, 2020

2011

Modeling Study of Impact of Surface Roughness on Flicker Noise in MOSFET.

Prafulla Galphade, Rasika Dhavse

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

2010

Reading a 4-Bit SLC NAND Flash Memory in 180nm Technology.

Nilesh Shah, Rasika Dhavse, Anand D. Darji

Proceedings of the Information and Communication Technologies - International Conference, 2010