Sudhanshu Janwadkar
Orcid: 0000-0001-7793-5822
According to our database1,
Sudhanshu Janwadkar
authored at least 2 papers
between 2020 and 2022.
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Bibliography
2022
Investigation and Analysis of Power Performance Area (PPA) Cards of Digital Multiplier Architectures.
J. Circuits Syst. Comput., 2022
2020
Implementation and Performance Evaluation of Novel Line Adder Architecture for Portable Systems : A Vedic Mathematics Approach.
Proceedings of the 2020 IEEE Region 10 Conference, 2020