We stand with Ukraine  

Sudhanshu Janwadkar

Orcid: 0000-0001-7793-5822

According to our database1, Sudhanshu Janwadkar authored at least 5 papers between 2020 and 2026.

Collaborative distances:
  • Dijkstra number2 of six.
  • Erdős number3 of five.

Timeline

Legend:

Book  In proceedings  Article  PhD thesis  Dataset  Other 

Links

On csauthors.net:

Bibliography

2026
Approximate Vedic Multiplier Based Digital Filter Architecture for Portable Biomedical Signal Acquisition.
[BibTeX]
[DOI]
Sudhanshu Janwadkar
,
Rasika Dhavse
Circuits Syst. Signal Process., January, 2026

2024
ASIC implementation of ECG denoising FIR filter by using hybrid Vedic-Wallace tree multiplier.
[BibTeX]
[DOI]
Sudhanshu Janwadkar
,
Rasika Dhavse
Int. J. Circuit Theory Appl., April, 2024

ASIC design of power and area efficient programmable FIR filter using optimized Urdhva-Tiryagbhyam Multiplier for impedance cardiography.
[BibTeX]
[DOI]
Sudhanshu Janwadkar
,
Rasika Dhavse
Microprocess. Microsystems, 2024

2022
Investigation and Analysis of Power Performance Area (PPA) Cards of Digital Multiplier Architectures.
[BibTeX]
[DOI]
Sudhanshu Janwadkar
,
Rasika Dhavse
J. Circuits Syst. Comput., 2022

2020
Implementation and Performance Evaluation of Novel Line Adder Architecture for Portable Systems : A Vedic Mathematics Approach.
[BibTeX]
[DOI]
Sudhanshu Janwadkar
,
Rasika Dhavse
Proceedings of the 2020 IEEE Region 10 Conference, 2020


  Loading...