Anand D. Darji

According to our database1, Anand D. Darji authored at least 26 papers between 2009 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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On csauthors.net:

Bibliography

2020
FPGA Implementation of MRMN with Step-Size Scaler Adaptive Filter for Impulsive Noise Reduction.
Circuits Syst. Signal Process., 2020

CSD Optimized DWT Filter for ECG Denoising.
Proceedings of the 2020 24th International Symposium on VLSI Design and Test (VDAT), 2020

An Efficient Dadda Multiplier using Approximate Adder.
Proceedings of the 2020 IEEE Region 10 Conference, 2020

2019
Assessment of interface traps in In<sub>0.53</sub>Ga<sub>0.47</sub>As FinFET with gate-to-source/drain underlap for sub-14 nm technology node to impede short channel effect.
IET Circuits Devices Syst., 2019

Stability Analysis of SRAM Designed Using In0.53Ga0.47As nFinFET with Underlap Region.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019

Implementation of High speed, Low PowerModified Vedic Multiplier and Its Application in Lifting based Discrete Wavelet Transform.
Proceedings of the TENCON 2019, 2019

2018
Automation of Timing Quality Checks and Optimization.
Proceedings of the VLSI Design and Test - 22nd International Symposium, 2018

2017
FPGA implementation of hardware efficient adaptive filter robust to impulsive noise.
IET Comput. Digit. Tech., 2017

Investigation of TCADs Models for Characterization of Sub 16 nm In _0.53 Ga _0.47 As FinFET.
Proceedings of the VLSI Design and Test - 21st International Symposium, 2017

2015
Multiplier-less pipeline architecture for lifting-based two-dimensional discrete wavelet transform.
IET Comput. Digit. Tech., 2015

Super-scale architecture enhancement of LEON3 core for DSP application.
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

High-performance multiplierless DCT architecture for HEVC.
Proceedings of the 19th International Symposium on VLSI Design and Test, 2015

2014
Dual-Scan Parallel Flipping Architecture for a Lifting-Based 2-D Discrete Wavelet Transform.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

High-performance hardware architectures for multi-level lifting-based discrete wavelet transform.
EURASIP J. Image Video Process., 2014

Hardware Efficient VLSI Architecture for 3-D Discrete Wavelet Transform.
Proceedings of the 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, 2014

Flipping-based high speed VLSI architecture for 2-D lifting DWT.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

Memory efficient VLSI architecture for lifting-based DWT.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014

Hardware efficient implementation of video capsule endoscopy.
Proceedings of the IEEE 3rd Global Conference on Consumer Electronics, 2014

2013
Watermarking Hardware Based on Wavelet Coefficients Quantization Method.
Circuits Syst. Signal Process., 2013

2012
Hardware efficient recursive VLSI architecture for multilevel lifting 2-D DWT.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
VLSI Implementation of Wavelet Based Robust Image Watermarking Chip.
Proceedings of the International Symposium on Electronic System Design, 2011

High speed VLSI architecture for 2-D lifting Discrete Wavelet Transform.
Proceedings of the 2011 Conference on Design and Architectures for Signal and Image Processing, 2011

2010
Reading a 4-Bit SLC NAND Flash Memory in 180nm Technology.
Proceedings of the Information and Communication Technologies - International Conference, 2010

VLSI Implementation of Balanced Binary Tree Decomposition Based 2048-Point FFT/IFFT Processor for Mobile WI-Max.
Proceedings of the 3rd International Conference on Emerging Trends in Engineering and Technology, 2010

VLSI Architecture of DWT Based Watermark Encoder for Secure Still Digital Camera Design.
Proceedings of the 3rd International Conference on Emerging Trends in Engineering and Technology, 2010

2009
Efficient Dual Domain Watermarking Scheme for Secure Images.
Proceedings of the ARTCom 2009, 2009


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