Ravi Mehta

According to our database1, Ravi Mehta authored at least 4 papers between 2011 and 2018.

Collaborative distances:
  • Dijkstra number2 of six.
  • Erdős number3 of six.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2018
A 12.5Gbps Transmitter for Multi-standard SERDES in 40nm Low Leakage CMOS Process.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

2016
A 0.5-4GHz Programmable-Bandwidth Fractional-N PLL for Multi-protocol SERDES in 28nm CMOS.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

2012
A programmable, multi-GHz, wide-range duty cycle correction circuit in 45nm CMOS process.
Proceedings of the 38th European Solid-State Circuit conference, 2012

2011
High voltage protection for USB transceivers in 45nm CMOS.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011


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