Sumantra Seth

According to our database1, Sumantra Seth authored at least 9 papers between 2004 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2022
A 5-Gb/s PAM4 Voltage Mode Transmitter with Current Mode Continuous Time Linear Equalizer.
Proceedings of the 35th International Conference on VLSI Design and 2022 21st International Conference on Embedded Systems, 2022

2021
Multi Voltage High Performance Bidirectional Buffer in a Low Voltage CMOS process.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
An Energy-Efficient 3Gb/s PAM4 Full-Duplex Transmitter With 2-Tap Feed Forward Equalizer.
IEEE Trans. Circuits Syst. II Express Briefs, 2020

2012
A differential self-biased slew rate controlled driver for accurate cross-over and rise-fall time matching.
Proceedings of the 38th European Solid-State Circuit conference, 2012

A programmable, multi-GHz, wide-range duty cycle correction circuit in 45nm CMOS process.
Proceedings of the 38th European Solid-State Circuit conference, 2012

2011
A low power high speed envelope detector for serial data systems in 45nm CMOS.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

High voltage protection for USB transceivers in 45nm CMOS.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2004
Design of RF Tuner for Cable Modem Applications.
Proceedings of the 17th International Conference on VLSI Design (VLSI Design 2004), 2004

An integrated linear RF power detector.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004


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