Raziyeh Salarifard

Orcid: 0000-0003-1323-6680

According to our database1, Raziyeh Salarifard authored at least 8 papers between 2014 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
An efficient hardware accelerator for NTT-based polynomial multiplication using FPGA.
J. Cryptogr. Eng., June, 2024

2023
Efficient Accelerator for NTT-based Polynomial Multiplication.
IACR Cryptol. ePrint Arch., 2023

2022
Secure and Low-Area Implementation of the AES Using FPGA.
ISC Int. J. Inf. Secur., 2022

2021
Low-Latency Keccak at any Arbitrary Order.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2021

2019
An Efficient Low-Latency Point-Multiplication Over Curve25519.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

2018
A Low-Latency and Low-Complexity Point-Multiplication in ECC.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

2016
High-Throughput Low-Complexity Unified Multipliers Over GF(2<sup>m</sup>) in Dual and Triangular Bases.
IEEE Trans. Circuits Syst. I Regul. Pap., 2016

2014
A robust SIFT-based descriptor for video classification.
Proceedings of the Seventh International Conference on Machine Vision, 2014


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