Amir Moradi

Affiliations:
  • Ruhr University Bochum, Germany


According to our database1, Amir Moradi authored at least 141 papers between 2005 and 2021.

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Bibliography

2021
Low-Latency Keccak at any Arbitrary Order.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2021

Second-Order SCA Security with almost no Fresh Randomness.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2021

Re-Consolidating First-Order Masking Schemes Nullifying Fresh Randomness.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2021

New First-Order Secure AES Performance Records.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2021

FIVER - Robust Verification of Countermeasures against Fault Injections.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2021

DL-LA: Deep Learning Leakage Assessment A modern roadmap for SCA evaluations.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2021

Countermeasures against Static Power Attacks - Comparing Exhaustive Logic Balancing and Other Protection Schemes in 28 nm CMOS -.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2021

Let's Take it Offline: Boosting Brute-Force Attacks on iPhone's User Authentication through SCA.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2021

The SPEEDY Family of Block Ciphers Engineering an Ultra Low-Latency Cipher from Gate Level for Secure Processor Architectures.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2021

Inconsistency of Simulation and Practice in Delay-based Strong PUFs.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2021

Low-Latency Hardware Masking of PRINCE.
IACR Cryptol. ePrint Arch., 2021

Generic Hardware Private Circuits - Towards Automated Generation of Composable Secure Gadgets.
IACR Cryptol. ePrint Arch., 2021

Automated Generation of Masked Hardware.
IACR Cryptol. ePrint Arch., 2021

Masked SABL: A Long Lasting Side-Channel Protection Design Methodology.
IEEE Access, 2021

Real-World Snapshots vs. Theory: Questioning the t-Probing Security Model.
Proceedings of the 42nd IEEE Symposium on Security and Privacy, 2021

Stealthy Logic Misuse for Power Analysis Attacks in Multi-Tenant FPGAs.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Automated Masking of Software Implementations on Industrial Microcontrollers.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

On the Impact of Aging on Power Analysis Attacks Targeting Power-Equalized Cryptographic Circuits.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020
Static Power Side-Channel Analysis - An Investigation of Measurement Factors.
IEEE Trans. Very Large Scale Integr. Syst., 2020

Side-Channel Hardware Trojan for Provably-Secure SCA-Protected Implementations.
IEEE Trans. Very Large Scale Integr. Syst., 2020

SKINNY-AEAD and SKINNY-Hash.
IACR Trans. Symmetric Cryptol., 2020

TI-PUF: Toward Side-Channel Resistant Physical Unclonable Functions.
IEEE Trans. Inf. Forensics Secur., 2020

Impeccable Circuits.
IEEE Trans. Computers, 2020

Spin Me Right Round Rotational Symmetry for FPGA-Specific AES: Extended Version.
J. Cryptol., 2020

Template attacks on nano-scale CMOS devices.
J. Cryptogr. Eng., 2020

Lightweight Ciphers on a 65 nm ASIC - A Comparative Study on Energy Consumption.
IACR Cryptol. ePrint Arch., 2020

SILVER - Statistical Independence and Leakage Verification.
IACR Cryptol. ePrint Arch., 2020

The Risk of Outsourcing: Hidden SCA Trojans in Third-Party IP-Cores Threaten Cryptographic ICs.
IACR Cryptol. ePrint Arch., 2020

BSPL: Balanced Static Power Logic.
IACR Cryptol. ePrint Arch., 2020

Remote Electrical-level Security Threats to Multi-Tenant FPGAs.
IEEE Des. Test, 2020

The Unpatchable Silicon: A Full Break of the Bitstream Encryption of Xilinx 7-Series FPGAs.
Proceedings of the 29th USENIX Security Symposium, 2020

Clock Glitch versus SIFA.
Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020

2019
Glitch-Resistant Masking Revisited or Why Proofs in the Robust Probing Model are Needed.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2019

Exploring the Effect of Device Aging on Static Power Analysis Attacks.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2019

Impeccable Circuits II.
IACR Cryptol. ePrint Arch., 2019

Automated Probe Repositioning for On-Die EM Measurements.
IACR Cryptol. ePrint Arch., 2019

A Comparison of Chi^2-Test and Mutual Information as Distinguisher for Side-Channel Analysis.
IACR Cryptol. ePrint Arch., 2019

A Note on Masking Generic Boolean Functions.
IACR Cryptol. ePrint Arch., 2019

Active Fences against Voltage-based Side Channels in Multi-Tenant FPGAs.
IACR Cryptol. ePrint Arch., 2019

CRAFT: Lightweight Tweakable Block Cipher with Efficient Protection Against DFA Attacks.
IACR Cryptol. ePrint Arch., 2019

Cryptographic Fault Diagnosis using VerFI.
IACR Cryptol. ePrint Arch., 2019

Cycle-Accurate Debugging of Multi-clock Reconfigurable Systems.
Proceedings of the 2019 International Conference on ReConFigurable Computing and FPGAs, 2019

A Comparison of χ <sup>2</sup>-Test and Mutual Information as Distinguisher for Side-Channel Analysis.
Proceedings of the Smart Card Research and Advanced Applications, 2019

2018
Leakage Detection with the x2-Test.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2018

Spin Me Right Round Rotational Symmetry for FPGA-Specific AES.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2018

Hardware Masking, Revisited.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2018

GliFreD: Glitch-Free Duplication Towards Power-Equalized Circuits on FPGAs.
IEEE Trans. Computers, 2018

Bitstream Fault Injections (BiFI)-Automated Fault Attacks Against SRAM-Based FPGAs.
IEEE Trans. Computers, 2018

A Note on Transitional Leakage When Masking AES with Only Two Bits of Randomness.
IACR Cryptol. ePrint Arch., 2018

Yet Another Size Record for AES: A First-Order SCA Secure AES S-box Based on GF(2<sup>8</sup>) Multiplication.
IACR Cryptol. ePrint Arch., 2018

Shuffle and Mix: On the Diffusion of Randomness in Threshold Implementations of Keccak.
IACR Cryptol. ePrint Arch., 2018

A First-Order SCA Resistant AES without Fresh Randomness.
IACR Cryptol. ePrint Arch., 2018

Remote Inter-Chip Power Analysis Side-Channel Attacks at Board-Level.
IACR Cryptol. ePrint Arch., 2018

An Inside Job: Remote Power Analysis Attacks on FPGAs.
IACR Cryptol. ePrint Arch., 2018

Threshold Implementation in Software - Case Study of PRESENT.
IACR Cryptol. ePrint Arch., 2018

Static Power Side-Channel Analysis - A Survey on Measurement Factors.
IACR Cryptol. ePrint Arch., 2018

Impeccable Circuits.
IACR Cryptol. ePrint Arch., 2018

Yet Another Size Record for AES: A First-Order SCA Secure AES S-Box Based on \(\mathrm {GF}(2^8)\) Multiplication.
Proceedings of the Smart Card Research and Advanced Applications, 2018

2017
Interdiction in practice - Hardware Trojan against a high-security USB flash drive.
J. Cryptogr. Eng., 2017

Strong 8-bit Sboxes with efficient masking in hardware extended version.
J. Cryptogr. Eng., 2017

On the Easiness of Turning Higher-Order Leakages into First-Order.
IACR Cryptol. ePrint Arch., 2017

Bit-Sliding: A Generic Technique for Bit-Serial Implementations of SPN-based Primitives - Applications to AES, PRESENT and SKINNY.
IACR Cryptol. ePrint Arch., 2017

SafeDRP: Yet Another Way Toward Power-Equalized Designs in FPGA.
IACR Cryptol. ePrint Arch., 2017

The First Thorough Side-Channel Hardware Trojan.
IACR Cryptol. ePrint Arch., 2017

SPARX - A side-channel protected processor for ARX-based cryptography.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
Leakage assessment methodology - Extended version.
J. Cryptogr. Eng., 2016

Bridging the Gap: Advanced Tools for Side-Channel Leakage Estimation beyond Gaussian Templates and Histograms.
IACR Cryptol. ePrint Arch., 2016

ParTI - Towards Combined Hardware Countermeasures against Side-Channel and Fault-Injection Attacks.
IACR Cryptol. ePrint Arch., 2016

Hiding Higher-Order Side-Channel Leakage - Randomizing Cryptographic Implementations in Reconfigurable Hardware.
IACR Cryptol. ePrint Arch., 2016

White-Box Cryptography in the Gray Box - A Hardware Implementation and its Side Channels.
IACR Cryptol. ePrint Arch., 2016

Side-Channel Analysis Protection and Low-Latency in Action - case study of PRINCE and Midori.
IACR Cryptol. ePrint Arch., 2016

Improved Side-Channel Analysis Attacks on Xilinx Bitstream Encryption of 5, 6, and 7 Series.
IACR Cryptol. ePrint Arch., 2016

Static Power Side-Channel Analysis of a Threshold Implementation Prototype Chip.
IACR Cryptol. ePrint Arch., 2016

Strong 8-bit Sboxes with Efficient Masking in Hardware.
IACR Cryptol. ePrint Arch., 2016

The SKINNY Family of Block Ciphers and its Low-Latency Variant MANTIS.
IACR Cryptol. ePrint Arch., 2016

Large laser spots and fault sensitivity analysis.
Proceedings of the 2016 IEEE International Symposium on Hardware Oriented Security and Trust, 2016

ParTI: Towards Combined Hardware Countermeasures against Side-Channeland Fault-Injection Attacks.
Proceedings of the ACM Workshop on Theory of Implementation Security, 2016

2015
Physical Security Evaluation of the Bitstream Encryption Mechanism of Altera Stratix II and Stratix III FPGAs.
ACM Trans. Reconfigurable Technol. Syst., 2015

A Hardware-Based Countermeasure to Reduce Side-Channel Leakage: Design, Implementation, and Evaluation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

Evaluating the Duplication of Dual-Rail Precharge Logics on FPGAs.
IACR Cryptol. ePrint Arch., 2015

Robust and One-Pass Parallel Computation of Correlation-Based Attacks at Arbitrary Order.
IACR Cryptol. ePrint Arch., 2015

Arithmetic Addition over Boolean Masking - Towards First- and Second-Order Resistance in Hardware.
IACR Cryptol. ePrint Arch., 2015

Leakage Assessment Methodology - a clear roadmap for side-channel evaluations.
IACR Cryptol. ePrint Arch., 2015

Achieving Side-Channel Protection with Dynamic Logic Reconfiguration on Modern FPGAs.
IACR Cryptol. ePrint Arch., 2015

Side-Channel Protection by Randomizing Look-Up Tables on Reconfigurable Hardware - Pitfalls of Memory Primitives.
IACR Cryptol. ePrint Arch., 2015

Affine Equivalence and its Application to Tightening Threshold Implementations.
IACR Cryptol. ePrint Arch., 2015

Assessment of Hiding the Higher-Order Leakages in Hardware - what are the achievements versus overheads?
IACR Cryptol. ePrint Arch., 2015

Side-Channel Security Analysis of Ultra-Low-Power FRAM-based MCUs.
IACR Cryptol. ePrint Arch., 2015

Side-channel attacks from static power: when should we care?
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Moments-Correlating DPA.
IACR Cryptol. ePrint Arch., 2014

Early Propagation and Imbalanced Routing, How to Diminish in FPGAs.
IACR Cryptol. ePrint Arch., 2014

Wire-Tap Codes as Side-Channel Countermeasure - an FPGA-based experiment.
IACR Cryptol. ePrint Arch., 2014

Side-Channel Leakage through Static Power - Should We Care about in Practice? -.
IACR Cryptol. ePrint Arch., 2014

Full-Size High-Security ECC Implementation on MSP430 Microcontrollers.
Proceedings of the Progress in Cryptology - LATINCRYPT 2014, 2014

Fault Sensitivity Analysis Meets Zero-Value Attack.
Proceedings of the 2014 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2014

2013
One Attack to Rule Them All: Collision Timing Attack versus 42 AES ASIC Cores.
IEEE Trans. Computers, 2013

Introducing proxy zero-knowledge proof and utilization in anonymous credential systems.
Secur. Commun. Networks, 2013

Detecting Hidden Leakages.
IACR Cryptol. ePrint Arch., 2013

Comprehensive Evaluation of AES Dual Ciphers as a Side-Channel Countermeasure.
Proceedings of the Information and Communications Security - 15th International Conference, 2013

Side-channel attacks on the bitstream encryption mechanism of Altera Stratix II: facilitating black-box analysis using software reverse-engineering.
Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

Attacking Atmel's CryptoMemory EEPROM with Special-Purpose Hardware.
Proceedings of the Applied Cryptography and Network Security, 2013

2012
Masked Dual-Rail Precharge Logic Encounters State-of-the-Art Power Analysis Methods.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Side channels as building blocks.
J. Cryptogr. Eng., 2012

On the Simplicity of Converting Leakages from Multivariate to Univariate - Case Study of a Glitch-Resistant Masking Scheme -
IACR Cryptol. ePrint Arch., 2012

Efficient and side-channel resistant authenticated encryption of FPGA bitstreams.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2012

Glitch-free implementation of masking in modern FPGAs.
Proceedings of the 2012 IEEE International Symposium on Hardware-Oriented Security and Trust, 2012

Statistical Tools Flavor Side-Channel Collision Attacks.
Proceedings of the Advances in Cryptology - EUROCRYPT 2012, 2012

Black-Box Side-Channel Attacks Highlight the Importance of Countermeasures - An Analysis of the Xilinx Virtex-4 and Virtex-5 Bitstream Encryption Mechanism.
Proceedings of the Topics in Cryptology - CT-RSA 2012 - The Cryptographers' Track at the RSA Conference 2012, San Francisco, CA, USA, February 27, 2012

How Far Should Theory Be from Practice? - Evaluation of a Countermeasure.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2012, 2012

2011
Side-Channel Resistant Crypto for Less than 2, 300 GE.
J. Cryptol., 2011

Improving the energy efficiency of reversible logic circuits by the combined use of adiabatic styles.
Integr., 2011

Collision Timing Attack when Breaking 42 AES ASIC Cores.
IACR Cryptol. ePrint Arch., 2011

On the Portability of Side-Channel Attacks - An Analysis of the Xilinx Virtex 4 and Virtex 5 Bitstream Encryption Mechanism.
IACR Cryptol. ePrint Arch., 2011

On the Vulnerability of FPGA Bitstream Encryption against Power Analysis Attacks - Extracting Keys from Xilinx Virtex-II FPGAs.
IACR Cryptol. ePrint Arch., 2011

Praktische Angriffe auf die Bitstromverschlüsselung von Xilinx FPGAs.
Datenschutz und Datensicherheit, 2011

Practical evaluation of DPA countermeasures on reconfigurable hardware.
Proceedings of the HOST 2011, 2011

Pushing the Limits: A Very Compact and a Threshold Implementation of AES.
Proceedings of the Advances in Cryptology - EUROCRYPT 2011, 2011

On the Power of Fault Sensitivity Analysis and Collision Side-Channel Attacks in a Combined Setting.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2011 - 13th International Workshop, Nara, Japan, September 28, 2011

Generic Side-Channel Countermeasures for Reconfigurable Devices.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2011 - 13th International Workshop, Nara, Japan, September 28, 2011

2010
Correlation-Enhanced Power Analysis Collision Attack.
IACR Cryptol. ePrint Arch., 2010

Practical Power Analysis Attacks on Software Implementations of McEliece.
Proceedings of the Post-Quantum Cryptography, Third International Workshop, 2010

Side-channel based Watermarks for Integrated Circuits.
Proceedings of the HOST 2010, 2010

Lightweight Cryptography and DPA Countermeasures: A Survey.
Proceedings of the Financial Cryptography and Data Security, 2010

2009
Vulnerability modeling of cryptographic hardware to power analysis attacks.
Integr., 2009

Dual-rail transition logic: A logic style for counteracting power analysis attacks.
Comput. Electr. Eng., 2009

A Comparative Study of Mutual Information Analysis under a Gaussian Assumption.
Proceedings of the Information Security Applications, 10th International Workshop, 2009

Charge recovery logic as a side channel attack countermeasure.
Proceedings of the 10th International Symposium on Quality of Electronic Design (ISQED 2009), 2009

Power Analysis of Single-Rail Storage Elements as Used in MDPL.
Proceedings of the Information, Security and Cryptology, 2009

KeeLoq and Side-Channel Analysis-Evolution of an Attack.
Proceedings of the Sixth International Workshop on Fault Diagnosis and Tolerance in Cryptography, 2009

Breaking KeeLoq in a Flash: On Extracting Keys at Lightning Speed.
Proceedings of the Progress in Cryptology, 2009

2008
Investigating the DPA-Resistance Property of Charge Recovery Logics.
IACR Cryptol. ePrint Arch., 2008

Information Leakage of Flip-Flops in DPA-Resistant Logic Styles.
IACR Cryptol. ePrint Arch., 2008

Secure Adiabatic Logic: a Low-Energy DPA-Resistant Logic Style.
IACR Cryptol. ePrint Arch., 2008

Physical Cryptanalysis of KeeLoq Code Hopping Applications.
IACR Cryptol. ePrint Arch., 2008

A secure and low-energy logic style using charge recovery approach.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

On the Importance of the Number of Fanouts to Prevent the Glitches in DPA-Resistant Devices.
Proceedings of the Advances in Computer Science and Engineering, 2008

On the Power of Power Analysis in the Real World: A Complete Break of the KeeLoqCode Hopping Scheme.
Proceedings of the Advances in Cryptology, 2008

2007
Power Analysis Attacks on MDPL and DRSL Implementations.
Proceedings of the Information Security and Cryptology, 2007

Compact and Secure Design of Masked AES S-Box.
Proceedings of the Information and Communications Security, 9th International Conference, 2007

2006
A Generalized Method of Differential Fault Attack Against AES Cryptosystem.
Proceedings of the Cryptographic Hardware and Embedded Systems, 2006

2005
Enhanced cross-diamond-hexagonal search algorithms for fast block motion estimation.
Proceedings of the Advanced Video and Signal Based Surveillance, 2005


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