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Reza Hashemian

Orcid: 0000-0002-0028-7078

According to our database1, Reza Hashemian authored at least 36 papers between 1990 and 2024.

Collaborative distances:
  • Dijkstra number2 of six.
  • Erdős number3 of five.

Timeline

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On csauthors.net:

Bibliography

2024
Extended "A Comprehensive and Unified Procedure for Symbolic Analysis of Analog Circuits".
[BibTeX]
[DOI]
Reza Hashemian
IEEE Trans. Circuits Syst. II Express Briefs, February, 2024

2022
Quick Access to Circuit Transfer Functions via NAM Determinant/Cofactors Using UaL Technique.
[BibTeX]
[DOI]
Reza Hashemian
IEEE Trans. Circuits Syst. II Express Briefs, 2022

A Comprehensive and Unified Procedure for Symbolic Analysis of Analog Circuits.
[BibTeX]
[DOI]
Reza Hashemian
IEEE Trans. Circuits Syst. I Regul. Pap., 2022

2021
Application of Nullors in Symbolic Single Port Transfer Functions Using Admittance Method.
[BibTeX]
[DOI]
Reza Hashemian
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
UaL Decomposition, an Alternative to the LU Factorization of MNA Matrices.
[BibTeX]
[DOI]
Reza Hashemian
IEEE Trans. Circuits Syst. II Express Briefs, 2020

s-Expanded Transfer Function using UaL Decomposition with Convolution & Deconvolution.
[BibTeX]
[DOI]
Reza Hashemian
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Constructing Circuit Transfer Functions directly from the State Equations, Using Convolutions.
[BibTeX]
[DOI]
Reza Hashemian
Proceedings of the 2020 IEEE International Conference on Electro Information Technology, 2020

2019
Design of Analog Circuits for Continuously Changing Constraints Using Fixator Norator Pairs.
[BibTeX]
[DOI]
Reza Hashemian
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019

2018
Amplifier Design for Specified Frequency Response Profiles Using Nullors-Hearing Aids, a Case Study.
[BibTeX]
[DOI]
Reza Hashemian
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A nullor approach to the design of analog circuits for a desirable performance.
[BibTeX]
[DOI]
Rohith Krishnan Pilla
,
S. Krishnakumar
,
Reza Hashemian
Microelectron. J., 2018

Fixator-Norator Pair Based Design of Feedback Networks for Analog Amplifier Circuits.
[BibTeX]
[DOI]
Rohith Krishnan Pilla
,
S. Krishnakumar
,
Reza Hashemian
J. Circuits Syst. Comput., 2018

A Comprehensive Nodal/Branch Circuit Analysis Including Fixator-Norator Pairs in Analog Circuits.
[BibTeX]
[DOI]
Reza Hashemian
Proceedings of the IEEE 61st International Midwest Symposium on Circuits and Systems, 2018

2017
Identifying and 3D Displaying Poles and Zeros in Analog Circuit Transfer Functions: Bode Surfaces.
[BibTeX]
[DOI]
Reza Hashemian
,
Mounika Vanga
,
Mahmoud Rahat
Circuits Syst. Signal Process., 2017

Nullors in amplifier design for bandwidth using multiple feedbacks.
[BibTeX]
[DOI]
Reza Hashemian
Proceedings of the 30th IEEE Canadian Conference on Electrical and Computer Engineering, 2017

2016
Finding poles and zeros in an analog circuit directly from its conductance matrix using eigenvalues.
[BibTeX]
[DOI]
Reza Hashemian
Comput. Electr. Eng., 2016

RC and RL to LC circuit conversion, and its application in poles and zeros identification.
[BibTeX]
[DOI]
Reza Hashemian
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016

Application of nullors in designing analog circuits for bandwidth.
[BibTeX]
[DOI]
Reza Hashemian
Proceedings of the 2016 IEEE International Conference on Electro Information Technology, 2016

2015
S-plane bode plots - identifying poles and zeros in a circuit transfer function.
[BibTeX]
[DOI]
Reza Hashemian
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

Identification and extraction of all real axis poles and zeros in RC and RL circuits.
[BibTeX]
[DOI]
Reza Hashemian
Proceedings of the IEEE International Conference on Electro/Information Technology, 2015

2014
Extraction of Poles and Zeros of an RC Circuit With Roots on the Real Axis.
[BibTeX]
[DOI]
Reza Hashemian
IEEE Trans. Circuits Syst. II Express Briefs, 2014

Fixator-Norator Pairs Versus Direct Analytical Tools in Performing Analog Circuit Designs.
[BibTeX]
[DOI]
Reza Hashemian
IEEE Trans. Circuits Syst. II Express Briefs, 2014

vLab, a high speed multi-accesses parallel processing remote laboratory access for FPGA design technology.
[BibTeX]
[DOI]
Kamran Ravanasa
,
Reza Hashemian
Proceedings of the IEEE International Conference on Electro/Information Technology, 2014

2012
Application of Fixator-Norator Pairs in Designing Active Loads and Current Mirrors in Analog Integrated Circuits.
[BibTeX]
[DOI]
Reza Hashemian
IEEE Trans. Very Large Scale Integr. Syst., 2012

2010
Local Biasing and the Use of Nullator-Norator Pairs in Analog Circuits Designs.
[BibTeX]
[DOI]
Reza Hashemian
VLSI Design, 2010

2008
Use of local biasing in designing analog integrated circuits.
[BibTeX]
[DOI]
Reza Hashemian
Proceedings of the 2008 IEEE International Conference on Electro/Information Technology, 2008

2007
FPGA e-Lab, a Technique to Remote Access a Laboratory to Design and Test.
[BibTeX]
[DOI]
Reza Hashemian
,
Jason Riddley
Proceedings of the IEEE International Conference on Microelectronic Systems Education, 2007

2006
Designing Analog Circuits with Reduced Biasing Power.
[BibTeX]
[DOI]
Reza Hashemian
Proceedings of the 13th IEEE International Conference on Electronics, 2006

2004
Condensed table of Huffman coding, a new approach to efficient decoding.
[BibTeX]
[DOI]
Reza Hashemian
IEEE Trans. Commun., 2004

A Hybrid Number System And Its Application In FPGA-DSP Technology.
[BibTeX]
[DOI]
Reza Hashemian
,
Bipin Sreedharan
Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'04), 2004

2003
Direct Huffman Coding And Decoding Using The Table Of Code-Lengths.
[BibTeX]
[DOI]
Reza Hashemian
Proceedings of the 2003 International Symposium on Information Technology (ITCC 2003), 2003

1995
Memory efficient and high-speed search Huffman coding.
[BibTeX]
[DOI]
Reza Hashemian
IEEE Trans. Commun., 1995

1994
Design of a 54-bit adder using a modified Manchester carry chain.
[BibTeX]
[DOI]
Reza Hashemian
Proceedings of the Fourth Great Lakes Symposium on Design Automation of High Performance VLSI Systems, 1994

1993
High speed search and memory efficient Huffman coding.
[BibTeX]
Reza Hashemian
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

1992
An alternative algorithm for high speed multiplication and addition using growing technique.
[BibTeX]
[DOI]
Reza Hashemian
Proceedings of the Second Great Lakes Symposium on VLSI, 1992

1990
Square Rooting Algorithms for Integer and Floatingg-Point Numbers.
[BibTeX]
[DOI]
Reza Hashemian
IEEE Trans. Computers, 1990

Parallel Addition Using Pipeline Structure.
[BibTeX]
Reza Hashemian
Proceedings of the 1990 International Conference on Parallel Processing, 1990


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