Roberto Maurino

Orcid: 0000-0003-2474-3995

According to our database1, Roberto Maurino authored at least 9 papers between 2000 and 2022.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2022
A 128ksps 120dB THD Low Noise Analog Front End.
Proceedings of the 48th IEEE European Solid State Circuits Conference, 2022

2019
A 6 $\mu$ W 95 dB SNDR Inverter Based $\Sigma\Delta$ Modulator With Subtractive Dithering and SAR Quantizer.
IEEE Trans. Circuits Syst. II Express Briefs, 2019

2017
A 19 nV/√Hz Noise 2-µ: V Offset 75-/micro;A Capacitive-Gain Amplifier With Switched-Capacitor ADC Driving Capability.
IEEE J. Solid State Circuits, 2017

5.7 A 19nV/√Hz-noise 2µV-offset 75µA low-drift capacitive-gain amplifier with switched-capacitor ADC driving capability.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

Subtractive dithering technique for delta-sigma modulator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2005
Quadrature ΣΔ modulators with a dynamic element matching scheme.
IEEE Trans. Circuits Syst. II Express Briefs, 2005

A 10mW 81dB cascaded multibit quadrature ΣΔ ADC with a dynamic element matching scheme.
Proceedings of the 31st European Solid-State Circuits Conference, 2005

2004
Multibit quadrature sigma-delta modulator with DEM scheme.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

2000
A 200-MHz IF 11-bit fourth-order bandpass ΔΣ ADC in SiGe.
IEEE J. Solid State Circuits, 2000


  Loading...