S. M. Rezaul Hasan

According to our database1, S. M. Rezaul Hasan authored at least 39 papers between 1995 and 2017.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2017
A Gene-Protein-miRNA Electronic Oscillator.
IEEE Trans. on Circuits and Systems, 2017

Optimized low-power CMOS active-electrode-pair for low-frequency multi-channel biomedical stimulation.
Microelectron. J., 2017

Computationally Minimized X-Part for FX Correlator in Big-Data Interferometers.
IEEE Access, 2017

2016
A VLSI Circuit Emulation of Chemical Synaptic Transmission Dynamics and Postsynaptic DNA Transcription.
IEEE Trans. VLSI Syst., 2016

Quadruply Split Cross-Driven Doubly Recycled gm-Doubling Recycled Folded Cascode for Microsensor Instrumentation Amplifiers.
IEEE Trans. on Circuits and Systems, 2016

New Low Glitch and Low Power DET Flip-Flops Using Multiple C-Elements.
IEEE Trans. on Circuits and Systems, 2016

A waveform generator circuit for extra low-frequency CMOS micro-power applications.
I. J. Circuit Theory and Applications, 2016

Dual-Band Waveform Generator With Ultra-Wide Low-Frequency Tuning-Range.
IEEE Access, 2016

2013
A 0.8V 40 Gb/s Novel CMOS Regulated Cascode Trans-impedance Amplifier for Optical Sensing Applications.
Signal Processing Systems, 2013

Design and Performance Analysis of a 866-MHz Low-Power Optimized CMOS LNA for UHF RFID.
IEEE Trans. Industrial Electronics, 2013

Integrated Circuit Modeling of Biocellular Post-Transcription Gene Mechanisms Regulated by MicroRNA and Proteasome.
IEEE Trans. on Circuits and Systems, 2013

Low-power compact composite field AES S-Box/Inv S-Box design in 65 nm CMOS using Novel XOR Gate.
Integr., 2013

2012
A 3-5 GHz Current-Reuse gm-Boosted CG LNA for Ultrawideband in 130 nm CMOS.
IEEE Trans. VLSI Syst., 2012

2011
Novel analysis and optimization of gm-boosted common-gate UWB LNA.
Microelectron. J., 2011

AC Dielectrophoresis Using Elliptic Electrode Geometry.
J. Sensors, 2011

2010
Analysis and Design of a Multistage CMOS Band-Pass Low-Noise Preamplifier for Ultrawideband RF Receiver.
IEEE Trans. VLSI Syst., 2010

A Low-voltage Scalable (1.8 V-0.75 V) CMOS Folded-cascode LC quadrature VCO for RF Receivers.
Journal of Circuits, Systems, and Computers, 2010

A micro-sequenced CMOS model for cell signalling pathway using G-protein and phosphorylation cascade.
IJCAT, 2010

Incremental delta-sigma modulators for temperature sensing applications.
IJCAT, 2010

2009
A Novel Low-voltage CMOS Variable Gain amplifier with Gain-Independent Input Impedance Matching for DTV Tuning Applications.
Journal of Circuits, Systems, and Computers, 2009

2008
A Novel Mixed-Signal Integrated Circuit Model for DNA-Protein Regulatory Genetic Circuits and Genetic State Machines.
IEEE Trans. on Circuits and Systems, 2008

Analog CMOS charge model for molecular redox electron-transfer reactions and bio-chemical pathways.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007
A PMOS-diode Differential Body-driven Offset compensated 0.5V.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

A Bias-Controlled Noise-Canceling CMOS Tuned Low Noise Amplifier for UWB Transceivers.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

2006
A Novel Current Feed-back Sub-Nano-Siemen Transconductance Circuit Suitable for Large Time-Constant Bio-medical Applications.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

Stability and Compensation Technique for a CMOS Amperometric Potentiostat Circuit for Redox Sensors.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

A Novel 16-bit CMOS Digitally Controlled Oscillator.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

2005
Design of a low-power 3.5-GHz broad-band CMOS transimpedance amplifier for optical transceivers.
IEEE Trans. on Circuits and Systems, 2005

A High Efficiency 3GHz 24-dBm CMOS Linear Power Amplifier for RF Application.
Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005

2004
A 4GHz Low-Power Folded-Cascode CMOS LC Quadrature VCO for RF Transceivers.
Proceedings of the International Conference on Embedded Systems and Applications, 2004

2003
A High Performance Wide-band CMOS Transimpedance Amplifier for Optical Transceivers.
Proceedings of the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 30 June, 2003

A 5GHz CMOS voltage-current feedback wide-band transimpedance amplifier for optical transceivers.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

A 5GHz CMOS digitally controlled oscillator with a 3GHz tuning range for PLL applications.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

2002
Reduction of Power Dissipation in Dynamic BiCMOS Logic Gates by Transistor Reordering.
VLSI Design, 2002

1999
An all Digital BiCMOS Phase Lock Loop for VLSI Processors.
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

1998
600 MHz Digitally Controlled BiCMOS Oscillator (DCO) for VLSI Signal Processing & Communication Applications.
Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

1997
A parallel processing VLSI BAM engine.
IEEE Trans. Neural Networks, 1997

1995
A VLSI BAM neural network chip for pattern recognition applications.
Proceedings of International Conference on Neural Networks (ICNN'95), Perth, WA, Australia, November 27, 1995

Improved singular value decomposition by using neural networks.
Proceedings of International Conference on Neural Networks (ICNN'95), Perth, WA, Australia, November 27, 1995


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