S. P. Joy Vasantha Rani
Orcid: 0000-0003-4094-2062
According to our database1,
S. P. Joy Vasantha Rani
authored at least 12 papers
between 2004 and 2022.
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Bibliography
2022
Approximate Multipliers Design Using Approximate Adders for Image Processing Applications.
J. Circuits Syst. Comput., 2022
2021
Wire-Length and Run-Time Optimization in FPGA Placement Using Hybrid Iterative Algorithms.
J. Circuits Syst. Comput., 2021
2020
Nonlinear Controller: Voltage Controlled PFC-Based Fuzzy MDPSM Controller with Predictive Input Voltage.
J. Circuits Syst. Comput., 2020
A Fast On-Chip Adaptive Genetic Algorithm Processor for Evolutionary FIR Filter Implementation Using Hardware-Software Co-Design.
J. Circuits Syst. Comput., 2020
Performance analysis of intrinsic embedded evolvable hardware using memetic and genetic algorithms.
Int. J. Bio Inspired Comput., 2020
2019
Efficient Design of ADC BIST with an Analog Ramp Signal Generation and Digital Error Estimation.
J. Circuits Syst. Comput., 2019
Automatic fault isolation and restoration of distribution system using JADE based Multi-Agents.
Turkish J. Electr. Eng. Comput. Sci., 2019
2018
2015
Pipelined hardware design of self tuning controller with on-chip parameter estimator.
Int. J. High Perform. Syst. Archit., 2015
2012
Proceedings of the Advances in Computing and Information Technology - Proceedings of the Second International Conference on Advances in Computing and Information Technology (ACITY) July 13-15, 2012, Chennai, India, 2012
2009
Field Programmable Gate Array based floating point hardware design of recursive k-means clustering algorithm for Radial Basis Function Neural Network.
Int. J. Intell. Syst. Technol. Appl., 2009
2004
Design of Neural Network on FPGA.
Proceedings of the International Conference on Embedded Systems and Applications, 2004