S. P. Joy Vasantha Rani
According to our database1, S. P. Joy Vasantha Rani authored at least 6 papers between 2004 and 2019.
Legend:Book In proceedings Article PhD thesis Other
Efficient Design of ADC BIST with an Analog Ramp Signal Generation and Digital Error Estimation.
Journal of Circuits, Systems, and Computers, 2019
An ADC BIST using on-chip ramp generation and digital ORA.
Microelectron. J., 2018
Pipelined hardware design of self tuning controller with on-chip parameter estimator.
Reconfigurable RNS FIR Filter Using Higher Radix Multiplier.
Proceedings of the Advances in Computing and Information Technology - Proceedings of the Second International Conference on Advances in Computing and Information Technology (ACITY) July 13-15, 2012, Chennai, India, 2012
Field Programmable Gate Array based floating point hardware design of recursive k-means clustering algorithm for Radial Basis Function Neural Network.
Design of Neural Network on FPGA.
Proceedings of the International Conference on Embedded Systems and Applications, 2004