S. P. Joy Vasantha Rani

According to our database1, S. P. Joy Vasantha Rani authored at least 6 papers between 2004 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2019
Efficient Design of ADC BIST with an Analog Ramp Signal Generation and Digital Error Estimation.
Journal of Circuits, Systems, and Computers, 2019

2018
An ADC BIST using on-chip ramp generation and digital ORA.
Microelectron. J., 2018

2015
Pipelined hardware design of self tuning controller with on-chip parameter estimator.
IJHPSA, 2015

2012
Reconfigurable RNS FIR Filter Using Higher Radix Multiplier.
Proceedings of the Advances in Computing and Information Technology - Proceedings of the Second International Conference on Advances in Computing and Information Technology (ACITY) July 13-15, 2012, Chennai, India, 2012

2009
Field Programmable Gate Array based floating point hardware design of recursive k-means clustering algorithm for Radial Basis Function Neural Network.
IJISTA, 2009

2004
Design of Neural Network on FPGA.
Proceedings of the International Conference on Embedded Systems and Applications, 2004


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