Sagar Satapathy

According to our database, Sagar Satapathy authored at least 8 papers between 2021 and 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2025

GATOR: A Graph Neural Network based Design Anomaly Predictor.

Sagar Satapathy, Dip Sankar Banerjee

Integr., 2025

DAPP: Delay Aware Power Prediction.

Sagar Satapathy, Dip Sankar Banerjee

Proceedings of the 26th International Symposium on Quality Electronic Design, 2025

2022

A Case for Amplifying Row Hammer Attacks via Cell-Coupling in DRAM Devices.

Kaustav Goswami, Shirshendu Das, Sagar Satapathy, Dip Sankar Banerjee

Proceedings of the 2022 International Symposium on Memory Systems, 2022

EFCSA: An Efficient Carry Speculative Approximate Adder with Rectification.

Saurabh Singh, Vishesh Mishra, Sagar Satapathy, Divy Pandey, Kaustav Goswami, Dip Sankar Banerjee, Babita Jajodia

Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

HPAM: An 8-bit High-Performance Approximate Multiplier Design for Error Resilient Applications.

Divy Pandey, Vishesh Mishra, Saurabh Singh, Sagar Satapathy, Babita Jajodia, Dip Sankar Banerjee

Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

AxLEAP: Enabling Low-Power Approximations Through Unified Power Format.

Sagar Satapathy, Saurabh Singh, Kaustav Goswami, Vishesh Mishra, Divy Pandey, Dip Sankar Banerjee

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

ART-MAC: Approximate Rounding and Truncation based MAC Unit for Fault-Tolerant Applications.

Vishesh Mishra, Divy Pandey, Saurabh Singh, Sagar Satapathy, Kaustav Goswami, Babita Jajodia, Dip Sankar Banerjee

Proceedings of the IEEE International Symposium on Circuits and Systems, 2022

2021

SAM: A Segmentation Based Approximate Multiplier for Error Tolerant Applications.

Divy Pandey, Saurabh Singh, Vishesh Mishra, Sagar Satapathy, Dip Sankar Banerjee

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021